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http://dx.doi.org/10.4313/JKEM.2006.19.2.126

Optimization of Capacitor Threshold VT Implantation for Planar P-MOS DRAM Cell  

Chang Sung-Keun (청운대학교 디지털방송공학과)
Kim Youn-Jang (매그나칩 반도체 DSD소자 2팀)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.19, no.2, 2006 , pp. 126-129 More about this Journal
Abstract
We investigated an optimized condition of the capacitor threshold voltage implantation(capacitor $V_T$ Implant) in planar P-MOS DRAM Cell. Several samples with different condition of the capacitor $V_T$ Implant were prepared. It appeared that for the capacitor $V_T$ Implant of $BF_2\;2.0{\times}l0^{13}\;cm^{-2}$ 15 KeV, refresh time is three times larger than that of the sample, in which capacitor $V_T$ Implant is in $BF_2\;1.0{\times}l0^{13}\;cm^{-2}$ 15 KeV. Raphael simulation revealed that the lowed maximum electric field and lowed minimum depletion capacitance ($C_{MIN}$) under the capacitor resulted in well refresh characteristics.
Keywords
P-MOS DRAM cell; Planar P-MOS; Refresh time; Raphael simulation;
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