• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.9
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• pp.30-37
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• 2000

In this paper, design and fabrication of miniature voltage-controlled oscillator(VCO) is discussed . Based on the two-port circuit analysis technique, VCO for 900MHz cellular mobile phone is designed and circuit parameters are optimized using the circuit simulator. Using the optimized design parameters, miniature VCO with 6${\times}$6${\times}$1.8 mm$^3$(0.065cc) dimensions is fabricated and experimented. Experimental results show that implemented VCO has -3.5 dBm output power level and 45MHz tunung range, respectively, and has -101.5dB/Hz Phase noise performance at 10 KHz frequency offset.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.295-301
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• 2008

Recently, the demand on mm-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the mm-wave frequency band have been traditionally implemented in III-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled mm-wave circuits realized in a Si CMOS technology. In this work, a 58 GHz CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a $0.13-{\mu}m$ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the mm-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 GHz with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 dBc/Hz at 5 MHz offset was achieved. The output power varied around -20 dBm over the measured tuning range. The circuit drew current (including buffer current) of 10 mA from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 dBc/Hz.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.503-504
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• 2006

This paper presents the design and fabrication of a LC voltage-controlled oscillator (VCO) using 1-poly 6-metal mixed signal CMOS process. To obtain the high-quality factor inductor in LC resonator, patterned-ground shields (PGS) is placed under the symmetric inductor to reduce the effect from image current of resistive Si substrate. Moreover, due to the incapability of using thick top metal layer of which the thickness is over $2{\mu}m$, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via materials along the metal traces is adopted. The circuit operated from 2.63 GHz to 3.09 GHz tuned by accumulation-mode MOS varactor. The corresponding tuning range was 460 MHz. The measured phase noise was -115 dBc/Hz @ 1MHz offset at 2.63 GHz carrier frequency and the current consumption and the corresponding power consumption were about 2.6 mA and 4.68 mW respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.5
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• pp.412-418
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• 2002

In this paper, the authors present the simulation results and the experimental considerations on the effects of the effects of the VCO oscillation characteristics caused by varying the length of the MSL and the composition capacitance of LC resonation circuity. Simulation was accomplished by nonlinear RF circuit simulator for designing and analyzing the RF characteristis of VCO. The samples with 3 different MSL lengths of which the length is 140mil, 280mil and 560mil respectively were fabricated by screen printing process. The oscillation frequency of each sample(VCO) was tuned to UHF band (750MHz~900MHz) by varying the capacitance of LC resonator circuit. The experimental results showed that the values of phase noise were -82, -93, -97[dBc/Hz] at 50[kHz] offset frequency, the pushing figures were 114, 94, 318[kHz] at applied voltage of $3\pm0.15$[V] and the harmonics were -21, -16, -13[dBc] for MSL lengths of 140mil 280mil, 560mil respectively. The frequency and output variation width were 779~898[MHz], -36~-33[dBm] for MSL with 140mil length; 818~836[MHz], -27.19~27.06[dBm] for 280mil; 751.54~751.198[MHz], -33.44~-33.31[dBm] for 560mil.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.34-41
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• 2011

This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 GHz (2.1 GHz to 3.5 GHz), it is 58 % at 2.4 GHz. An effective frequency resolution is 0.14 kHz/LSB. The proposed DCO is implemented in 0.13 ${\mu}m$ CMOS process. The total power consumption is 6.6 mW from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.974-982
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• 2009

Photomixing techniques beating two optical signals with different wavelengths and strong correlations are also very useful techniques to make a continuous wave(CW) signals in the range of millimeter(mm) and terahertz(THz) frequencies. An optical double sideband-suppressed carrier(DSB-SC) technique is one of the popular techniques to generate two optical signals with different wavelengths and strong correlations. DSB-SC signals with strong correlations are generated by a CW modulation of an optical carrier with a local oscillator and an optical modulator. In the previous parers related the DSB-SC for producing the CW signals within the range of mm and THz frequencies, there have been no reports why the optical carrier should suppress. In order to clear that, we have analyzed and measured the characteristics of the mm-wave CW signals made by the DSB-SC photomixing in this paper. From our analysis and measurement results, compared with the case of the DSB with the maximized optical carrier, the power and phase noise have improved about 23.9 dB and 21 dBc/Hz(@ 1 MHz offset frequency) in the case of the DSB with the minimized optical carrier (that is to say, the DSB-SC). Consequently, it is evident reason that the optical carrier should sufficiently suppress to obtain the mm-wave CW signals with the high power and low noise. This paper has given very helpful data to make mm- and THz-wave CW signals using photomixing techniques with the DSB-SC because the reason why the optical carrier should be suppressed is reported in this paper based on the numerical and experimental results.

• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.1
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• pp.31-38
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• 2024

The digital phase-locked loop(DPLL) is one of the circuits composed of a digital detector, digital loop filter, voltage-controlled oscillator, and divider as a fundamental circuit, widely used in many fields such as electrical and circuit fields. A state estimator using various mathematical algorithms is used to improve the performance of a digital phase-locked loop. Traditional state estimators have utilized Kalman filters of infinite impulse response state estimators, and digital phase-locked loops based on infinite impulse response state estimators can cause rapid performance degradation in unexpected situations such as inaccuracies in initial values, model errors, and various disturbances. In this paper, we propose a two-layer Frobenius norm-based finite impulse state estimator to design a new digital phase-locked loop. The proposed state estimator uses the estimated state of the first layer to estimate the state of the first layer with the accumulated measurement value. To verify the robust performance of the new finite impulse response state estimator-based digital phase locked-loop, simulations were performed by comparing it with the infinite impulse response state estimator in situations where noise covariance information was inaccurate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.