• Journal of the Optical Society of Korea
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• v.20 no.5
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• pp.623-627
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• 2016

A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recovery circuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features of the optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automatically optimized according to the bit rates. The prototype receiver has −23.7 dBm to −15.4 dBm of optical sensitivity for 10⁻⁹ bit error rate with constant conversion gain around all target bit rates from 1.62Gbps to 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.

• Current Optics and Photonics
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• v.7 no.2
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• pp.166-175
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• 2023

We theoretically analyze and experimentally demonstrate a polarization-diversified four-channel optical demultiplexer (DeMUX) comprising a hybrid mode conversion-type polarization splitter rotator (PSR) and delayed Mach-Zehnder interferometer optical DeMUX for use in coarse wavelength division multiplexing (CWDM)-based optical interconnect applications. The Si wire-based device fabricated by a complementary metal-oxide semiconductor-compatible process exhibited nearly the same filter spectral response irrespective of the input polarization state under the PSR. The device had an extremely low insertion loss of <1.0 dB, polarization-dependent loss of <1.0 dB, and interchannel imbalance of <0.5 dB, suppressing unwanted wavelength and polarization crosstalk from neighboring channels of <-20 dB at each peak transmission channel grid.

• ETRI Journal
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• v.39 no.5
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• pp.632-642
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• 2017

Digital all-optical parallel computing is an important research direction and spans conventional devices and convergent nano-optics deployments. Optical bus-based interconnects provide interesting aspects such as relative information communication speed-up or slow-down between optical signals. This aspect is harnessed in the newly proposed All-Optical Linear Array with a Reconfigurable Pipelined Bus System (OLARPBS) model. However, the physical realization of such communication interconnects needs to be considered. This paper considers spatial layouts of processing elements along with the optical bus light paths that are necessary to realize the corresponding interconnection requirements. A metric in terms of the degree of required physical constraint is developed to characterize the variety of possible solutions. Simple algorithms that determine spatial layouts are given. It is shown that certain communication interconnection structures have associated intrinsic topologies.

• Electronics and Telecommunications Trends
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• v.37 no.2
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• pp.42-52
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• 2022

Intra- and inter- datacenter data traffic is rapidly increasing due to the spread of smart devices, cloud computing, and non-face-to-face services. Recently, 400-Gbps optical transceivers based on 100-Gbps/channel have been released primarily by major overseas companies. Various solutions for next-generation datacenter interconnect are being proposed by international standardization and multiple source agreement groups. Following this trend, ETRI has developed a 400-Gbps optical transmission/reception engine using 100-Gbps/channel light sources and photodetectors as well as a silica-based AWG. In the future, technologies of optical devices and components for intra-datacenter communication are expected to be developed based on a data rate of 200-Gbps/channel. Thus, 1.6-Tbps class optical transceivers will be released.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.854-859
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• 2016

Recently, GeSn is drawing great deal of interests as one of the candidates for group-IV-driven optical interconnect for integration with the Si complementary metal-oxide-semiconductor (CMOS) owing to its pseudo-direct band structure and high electron and hole mobilities. However, the large lattice mismatch between GeSn and Si as well as the Sn segregation have been considered to be issues in preparing GeSn on Si. In this work, we deposit the GeSn films on Si by DC magnetron sputtering at a low temperature of $250^{\circ}C$ and characterize the thin films. To reduce the stresses by GeSn onto Si, Ge buffer deposited under different processing conditions were inserted between Si and GeSn. As the result, polycrystalline GeSn domains with Sn atomic fraction of 6.51% on Si were successfully obtained and it has been demonstrated that the Ge buffer layer deposited at a higher sputtering power can relax the stress induced by the large lattice mismatch between Si substrate and GeSn thin films.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.5
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• pp.331-337
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• 2014

Ge is becoming an increasingly popular semiconductor material with high Si compatibility for on-chip optical interconnect technology. For a better manifestation of the meritorious material properties of Ge, its surface treatment should be performed satisfactorily before the electronic and photonic components are fabricated. Ex-situ rapid thermal annealing (RTA) processes with different gases were carried out to examine the effects of the annealing gases on the thin-film quality of Ge grown epitaxially on Si substrates. The Ge-on-Si samples were prepared in different structures using the same equipment, reduced-pressure chemical vapor deposition (RPCVD), and the samples annealed in $N_2$, forming gas (FG), and $O_2$ were compared with the unannealed (deposited and only cleaned) samples to confirm the improvements in Ge quality. To evaluate the thin-film quality, room-temperature photoluminescence (PL) measurements were performed. Among the compared samples, the $O_2$-annealed samples showed the strongest PL signals, regardless of the sample structures, which shows that ex-situ RTA in the $O_2$ environment would be an effective technique for the surface treatment of Ge in fabricating Ge devices for optical computing systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.25-32
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• 2009

Recently, research for Network-on-chip(NoC) is progressing. However, due to the increase of system complexity and demand on high performance, conventional copper-based electrical interconnect would be faced with the design limitation of performance, power, and bandwidth. As an alternative to these problems, combined use of Electrical Interconnects(EIs) and Optical Interconnects(OIs) has been introduced. In this paper we propose efficient routing optimization strategy and hybrid switch architecture, which use OIs for critical path and EIs for non-critical path. The proposed method shows up to 25% performance improvement and 38% power reduction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.64-64
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• 2009

As the advanced packaging technology developing, Copper electro-plating processing has be wildly utilized in the semiconductor interconnect technique. Chemical solution monitoring methods, including PH and gravity measurement exist in industry, but economical and practical real-time monitoring has not been achieved yet. Red-green-blue (RGB) color sensor can successfully monitor the condition of $CuSO_4$ solution during electric copper plating process. Comparing the intensity variations of the RGB data and optical spectroscopy data, strong correlation between two in-situ sensors have shown.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.89-103
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.120-136
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.