• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.3
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• pp.165-169
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• 2008

Analog-to-Digital converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental converters provide a solution for such measurement applications, as they retain most of the advantages of conventional ${\Delta}{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. Most of the previous research on incremental converters was for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth ac signals is discussed. A design methodology to optimize the signal-to-quantization+thermal noise ratio of multiplexed IDC is presented. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.317-323
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• 1998

A synchronization is important element not only wire communication but also wireless communication. Especially, In SS(Spread Spectrum) communication method used GPS(Global Positioning System) synchronization is more important. A synchronous oscillator(SO) is a network which synchronizes, tracks, filter, amplifies and divides (if necessary) in a single process. Without an input signal, the SO is a free-running oscillator, oscillating at a frequency $w_0$, but phase changes $180^{\circ}$ within tracking range of SO. Therefore CPSO was used for this problem. The coherent phase synchronous oscillator(CPSO) is created by adding two external loops to the SO and has a wider tracking bandwidth and a zero-offset phase response (coherent) while maintaining the SO properties of high signal-to-rejection and fast frequency acquisition times. Therefore phase between input signal and output signal is synchronized. In this paper, GPS data recovery circuit has applied CPSO using front reference characters and has certified an excellent data recovery capability.

• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.4
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• pp.485-491
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• 2014

An Antenna & RF system for a fly-away satcom terminal application on ka-band is presented in this paper. The Fly-away satellite terminal can be moved and operated by two person and adapt automatic satellite tracking system in order to decrease the tracking time. Additionally, for low-power consumption, compact size and light-weight, a dual reflector antenna is constructed using dual-offset gregorian antenna structure. For minimize weight, the reflector of the antenna is made of Magnesium. For low-power consumption and light-weight, the pHEMT MMIC compound devices is utilized. The Electronic Band-Gap(EBG) Low-Pass Filter(LPF) is designed for harmonic rejection. In the receiving part, Low-Noise Block converter(LNB) structure is designed for compact and lightweight. In this paper, fly-away satcom terminal with low-power consumption, compact size and light-weight is described with antenna system and RF system performances. Through the experimentation, fly-away terminal's EIRP is more than 50dBW, G/T is more than $17dB/^{\circ}K$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.2
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• pp.309-314
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• 2008

Analog-to-digital converters(ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental(integrating) data converters(IDCs) provide a solution for such measurement applications, as they retain most of the advantages of conventional $\Delta{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth AC signals over multi-channel is discussed. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11C
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• pp.1085-1097
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• 2009

We present a structure and design method of the D8PSK modem compatible with the VDL mode-2 standard and performance test results of the developed modem. In VDL mode-2, the raised cosine filter is used only in the transmitter and a general low pass filter is used in the receiver. Consequently, we can not achieve ISI reduction but can have better spectrum characteristics. Although there is 1~2 dB performance degradation with an un-matched filter compared to that with a matched filter, it is more important to minimize adjacent channel interference in narrow band communications. The transmit signal is generated digitally to avoid the problems(I/Q imbalance and DC offset etc.) of analog modulators. In addition the digital down converter using digital IF sampling technique is adopted for the receiver. This paper contains the overall configuration, design method and simulation results based in part on the previously proposed structures and algorithms. It is confirmed that the modem transmits and receives messages successfully at a speed of max. 870 km/h over ranges of up to 310 km through the ground and in-flight communication tests.

• Journal of Navigation and Port Research
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• v.30 no.10 s.116
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• pp.847-853
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• 2006

In this paper, we designed VCO(voltage controlled oscillator} that is composed of a dielectric resonator and a varactor diode, and the PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The results at 12.05 GHz show the output power is 13.54 dBm frequency tuning range approximately +/- 7.5 MHz, and power variation over the tuning range less than 0.2 dB, respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 dBc/Hz at 100 kHz offset from carrier, and The second harmonic suppression is less than -41.49 dBc. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.

• Journal of Broadcast Engineering
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• v.4 no.2
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• pp.103-118
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• 1999

This paper analyzes the performance of symbol timing recovery and equalizer in 8VSB digital terrestrial TV receiver under various multipath signals and proposes equalization techniques which improve indoor reception performance. Data segment sync is used for symbol timing recovery and timing offset is measured for echoes of various delays and amplitudes by using symbol timing detection filter whose pattern is +1. +1. -1. and -1. Measured timing offsets were below 10% for long echoes with more than 5 symbol delay and above 30% for short echoes with around 1 symbol delay. Indoor reception is always more challenging than outdoor reception due to lower signal strength. large and short multipaths. and moving interfering objects. So it is considered to use FSE (Fractionally Spaced Equalizer) which is very robust to timing offset and blind equalizer which can update equalizer tap coefficients even by information data. We compare the performance of conventional DFE (Decision Feedback Equalizer) and FSE-DFE using LMS algorithm and Stop and Go algorithm for the indoor reception. Experiments reveals FSE has excellent performance for large timing offset and Stop and Go algorithm shows good performance for Doppler shift. so we propose to use FSE-DFE structure with Stop and Go algorithm for the reliable indoor reception.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.271-274
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• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.423-429
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• 2007

The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1077-1083
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• 2009

To reject the Doppler frequency spectrum dispersion of clutter caused by high-speed antenna rotation of MTI radar system due to terrain characteristics, signal processing parameters(MTI filter constant, M/N detector ration, K-factor and offset of CFAR) are adjusted for the optimal elimination of the ground clutter. For this investigation, logging equipment is designed and utilized for the collection of classified ground clutter data. Test case is devised through Matlab simulation for the classified analysis and optimization of clutter rejection. Then indoor radar test and outside test in accordance with terrain characteristics are repeatedly performed for the verification of the test. This whole process is through the evolutional development model and repeated for the optimization. Final result is that ground-clutter rejection capability is 5.6 times(7.5 dB) better than that of existing radar system.