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http://dx.doi.org/10.5394/KINPR.2006.30.10.847

Design and Fabrication of on Oscillator with Low Phase Noise Characteristic using a Phase Locked Loop  

Park, Chang-Hyun (Division of Marine Electronic & comm Eng, Mokpo National Maritime University)
Kim, Jang-Gu (Department of Electronics and Applied Physics, Japan, Tokyo Institute of Technology)
Choi, Byung-Ha (Division of Marine Electronic & comm. Eng, Mokpo National Maritime University)
Abstract
In this paper, we designed VCO(voltage controlled oscillator} that is composed of a dielectric resonator and a varactor diode, and the PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The results at 12.05 GHz show the output power is 13.54 dBm frequency tuning range approximately +/- 7.5 MHz, and power variation over the tuning range less than 0.2 dB, respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 dBc/Hz at 100 kHz offset from carrier, and The second harmonic suppression is less than -41.49 dBc. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.
Keywords
VCO; PLDRO; Sampling phase detector; Loop filter; Phase noise; PLL;
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