• Journal of Broadcast Engineering
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• v.14 no.4
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• pp.518-536
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• 2009

To verify the performance of a Distributed Translator Network(DTxR) system in the real world conditions, 5 legacy DTV broadcasting repeater sites were implemented with 5 DTxR systems and field-tested by the DTV field test truck. The 4 DTV broadcasting repeater sites are selected in congested areas where their service areas are overlapped and the 5th site is deviated from the other sites to examine the effect of long-delayed multipath signals. First of all, we checked the receiving signal of the main station that used as a transmitting signal in 5 DTxR systems on the pre-selected 60 test points and tested every case of a DTxR system's on & off except 1 repeater site due to the already built-in DTV repeater system. The test items are received signal electric field strength, noise margin, ease of reception and subjective evaluation of the picture quality for received signals. We used 3rd, 5th, and 6th generation DTV receivers to examine the differences of the receivability by each generation of DTV receivers. Reviewing the test results, we conclude that the DTxR system can be adopted in the current DTV Repeater sites and it could improve the quality and receivability of the main signals by extending the service areas and enhancing the signal levels in the shadow areas without using the extra broadcasting channels.

• The Korean Journal of Financial Management
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• v.20 no.1
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• pp.191-212
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• 2003

Recently, there is a growing body of literature that suggests that information inefficiency is one of the causes of the asymmetric volatility. If this explanation for the asymmetric volatility is appropriate, then innovations, such as the introduction of futures, may be expected to impact the asymmetric volatility of stock market. As transaction costs and margin requirements in the futures market are lower than those in the spot market, new information is transmitted to futures prices more quickly and affects spot prices through arbitrage trading with spots. Also, the merit of the futures market may attract noise traders away from the spot market to the futures market. This study examines the impact of futures on the asymmetry of stock market volatility. If the asymmetric volatility is significant lower post-futures and exist in the futures market, it has validity that the asymmetric volatility is caused by information inefficiency in the spot market. The data examined are daily logarithmic returns on KOSPI 200 stock price index from January 4, 1993 to December 26, 2000. To examine the existence of the asymmetric volatility in the futures market, logarithmic returns on KOSPI 200 futures are used from May 4, 1996 to December 26, 2000. We used a conditional mode of TGARCH(threshold GARCH) of Glosten, Jagannathan and Runkel(1993). Pre-futures the spot market exhibits significant asymmetric responses of volatility to news and post-futures asymmetries are significantly lower, irrespective of bear market and bull market. The results suggest that the introduction of stock index futures has an effect on the asymmetric volatility of the spot market and are inconsistent with leverage being the sole explanation of asymmetry. However, it is found that the volatility of futures is not so asymmetric as expected.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.10
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• pp.629-636
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• 2016

This study presents the development of an acid resistance velocity sensor that is used for measuring velocity inside a copper sulfate plating bath. First, researchers investigated the acid resistance coating to confirm the suitability of the anti-acid sensor in a very corrosive environment. Then, researchers applied signal processing methods to reduce noise and amplify the signal. Next, researchers applied a pressure-resistive sensor with an operation amplifier (Op Amp) and low-pass filter with high impedance to match the output voltage of a commercial flowmeter. Lastly, this study compared three low-pass filters (Bessel, Butterworth and Chebyshev) to select the appropriate signal process circuit. The results show 0.0128, 0.0023, and 5.06％ of the mean square error, respectively. The Butterworth filter yielded more precise results when compared to a commercial flowmeter. The acid resistive sensor is capable of measuring velocities ranging from 2 to 6 m/s with a 2.7％ margin of error.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1737-1743
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• 2006

OCR(On channel repeater) provides the high frequency reuse efficiency for allocating frequency bands to repeaters because the frequency of input and output signals of OCRs is the same. However the oscillation probability of OCRs is high due to the same input and output frequency. In order to prevent a repeater from oscillating, we must keep the antenna isolation higher than the gain of the repeater with a some margin. In this paper we simulated the effects of the amplitude, phase and time delay of feedback signals (m the characteristics of non-regeneration OCR. Simulation results show that the highest probability of oscillation is occurred when the gain of a repeater is the same value of the isolation. From the simulation results, we know that the phase of feedback signals can be adjusted to reduce the possibility of oscillation if a non-regeneration repeater has a narrow operation bandwidth or a signal bandwidth is narrow. As the time delay increases, the probability of oscillation and the fluctuation of gain over a certain frequency band increase also. The effects of the amplitude and phase of feedback signals on S/N of 8-VSB signal for generation and non-generation repeater were tested. The measured results show that the set-top can receive 8-VSB signal when the received signal power is $17{\sim}18dB$ higher than the noise power. When the isolation is almost same as the gain of the repeater, then the set-top can not receive 8-VSB signals due to the oscillation of the repeater. And the phase of feedback signals affects S/N at the output of the repeater when the isolation is $11.75{\sim}13.75dB$ larger than the gain of the repeater. In this case the set-top can not receive 8-VSB signal of at $48^{\circ}\;and\;347^{\circ}$ of the phase of feedback signals. However the phase of feedback signals can not affect the S/N of 8-VSB signals of the generation repeater because of the demodulation and modulation process of the generation repenter. The set-top can not receive 8-VSB signals when the amplitude of feedback signals is $12.6{\sim}13.6dB$ larger than the wanted signal power at the input port of the repeater. It's because that the amplitude of feedback signals saturates the front end of the repeater.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.