• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.59-63
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• 2015

This paper discusses the capacitance-voltage method in Metal-Oxide-Nitride-Oxide-Silicon (MONOS) devices to analyzed the characteristics of the top oxide/nitride, nitride/bottom oxide interface trap distribution. In the CV method, nitride trap density can be calculated based on the program characteristics of the nitride thickness variations. By applying this method, silicon rich nitride device found to have a larger trap density than stoichiometric nitride device. This result is consistent with previous studies. If this comparison analysis can be expected to result in improved reliability of the SONOS flash memory.

• Transactions on Electrical and Electronic Materials
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• v.5 no.6
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• pp.227-232
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• 2004

We investigated a nonvolatile nanomemory element based on boron nitride nanopeapods using molecular dynamics simulations. The studied system was composed of two boron-nitride nanotubes filled Cu electrodes and fully ionized endo-fullerenes. The two boron-nitride nanotubes were placed face to face and the endo-fullerenes came and went between the two boron-nitride nanotubes under alternatively applied force fields. Since the endo-fullerenes encapsulated in the boron-nitride nanotubes hardly escape from the boron-nitride nanotubes, the studied system can be considered to be a nonvolatile memory device. The minimum potential energies of the memory element were found near the fullerenes attached copper electrodes and the activation energy barrier was $3{\cdot}579 eV$. Several switching processes were investigated for external force fields using molecular dynamics simulations. The bit flips were achieved from the external force field of above $3.579 eV/{\AA}$.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.134-137
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• 2019

In this paper, the data retention characteristics were analyzed to find out the thickness effect on the trap energy distribution of silicon nitride in the silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. The nitride films were prepared by low pressure chemical vapor deposition (LPCVD). The flat band voltage shift in the programmed device was measured at the elevated temperatures to observe the thermal excitation of electrons from the nitride traps in the retention mode. The trap energy distribution was extracted using the charge decay rates and the experimental results show that the portion of the shallow interface trap in the total nitride trap amount including interface and bulk trap increases as the nitride thickness decreases.

• Journal of IKEEE
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• v.25 no.4
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• pp.770-773
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• 2021

In this paper, the retention characteristics of 3D NAND flash memory applied with tapering and ferroelectric (HfO₂) structure were analyzed after programming operation. Electrons trapped in nitride are affected by lateral charge migration over time. It was confirmed that more lateral charge migration occurred in the channel thickened by tapering of the trapped electrons. In addition, the Oxide-Nitride-Ferroelectric (ONF) structure has better lateral charge migration due to polarization, so the change in threshold voltage (V_th) is reduced compared to the Oxide-Nitride-Oxide (ONO) structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.1
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• pp.24-29
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• 2005

Silicon nitride cantilevers integrated with silicon heaters and piezoelectric sensors were developed for the scanning probe microscope (SPM) based data storage application. These nitride cantilevers are expected to have better mechanical stability and uniformity of initial bending than the previously developed silicon cantilevers. Data bits of 40 nm in diameter were recorded on PMMA film and the sensitivity of the piezoelectric sensor was 0.615 fC/nm, meaning that indentations less than 20 nm in depth can be detected. For high speed operation, $128{\times}128$ cantilever array was developed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.85-90
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• 2012

In this paper, we compared and analyzed 3D silicon-oxide-nitride-oxide-silicon (SONOS) multi layer flash memory devices fabricated on nitride or oxide layer, respectively. The device fabricated on nitride layer has inferior electrical properties than that fabricated on oxide layer. However, the device on nitride layer has faster program / erase speed (P/E speed) than that on the oxide layer, although having inferior electrical performance. Afterwards, to find out the reason why the device on nitride has faster P/E speed, 1/f noise analysis of both devices is investigated. From gate bias dependance, both devices follow the mobility fluctuation model which results from the lattice scattering and defects in the channel layer. In addition, the device on nitride with better memory characteristics has higher normalized drain current noise power spectral density ($S_{ID}/I^2_D$>), which means that it has more traps and defects in the channel layer. The apparent hooge's noise parameter (${\alpha}_{app}$) to represent the grain boundary trap density and the height of grain boundary potential barrier is considered. The device on nitride has higher ${\alpha}_{app}$ values, which can be explained due to more grain boundary traps. Therefore, the reason why the devices on nitride and oxide have a different P/E speed can be explained due to the trapping/de-trapping of free carriers into more grain boundary trap sites in channel layer.

• Transactions of the Society of Information Storage Systems
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• v.1 no.1
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• pp.73-77
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• 2005

In this paper, a new silicon nitride cantilever integrated with silicon heater and piezoelectric sensor has been firstly developed to improve the uniformity of the initial bending and the mechanical stability of the cantilever array for thermo-piezoelectric SPM(scanning probe microscopy) -based data storages. This nitride cantilever shows thickness uniformity less than $2\%$. Data bits of 40 nm in diameter were recorded on PMMA film. The sensitivity of the piezoelectric sensor was 0.615 fC/nm after poling the PZT layer. For high speed operation, 128${\times}$128 probe array was developed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.56-62
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• 1992

This paper is analyzed the charge trapping and electrical properties of 0(Oxide), NO(Nitrided oxide) and ONO(Reoxidized nitrided oxide) as dielectric films in MIS structures. We have processed bottom oxide and top oxide by the thermal method, and nitride(Si$_{3}N_{4}$) by the LPCVD(Low Pressure Chemical Vapor Deposition) method on P-type(100) Silicon wafer. We have studied the charge trapping properties of the dielectrics by using a computer controlled DLTS system. All of the dielectric films are shown peak nearly at 300K. Those are bulk traps. Many trap densities which is detected in NO films, but traps. Many trap densities which is detected in NO films. Varing the nitride thickness, the trap densities of thinner nitride is decreased than the thicker nitride. Finally we have found that trap densities of ONO films is affected by nitride thickness.

• Journal of Power Electronics
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• v.9 no.1
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• pp.36-42
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• 2009

This paper presents a review of an improved high power-high frequency III-V wide bandgap (WBG) semiconductor device, Gallium Nitride (GaN). The device offers better efficiency and thermal management with higher switching frequency. By having higher blocking voltage, GaN can be used for high voltage applications. In addition, the weight and size of passive components on the printed circuit board can be reduced substantially when operating at high frequency. With proper management of thermal and gate drive design, the GaN power converter is expected to generate higher power density with lower stress compared to its counterparts, Silicon (Si) devices. The main contribution of this work is to provide additional information to young researchers in exploring new approaches based on the device's capability and characteristics in applications using the GaN power converter design.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.192-192
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• 2012

The next generation electronics need to not only be smaller but also be more flexible. To meet such demands, electronic devices using two dimensional (2D) atomic crystals like graphene, hexagonal boron nitride (h-BN), molybdenum disulfate ($MoS_2$) and organic thin film have been studied intensely. In this talk, I will demonstrate the $MoS_2$ field effect transistor (FET) toward performance enhancement by insulating h-BN substrate.