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http://dx.doi.org/10.5573/ieie.2015.52.8.059

Analysis of Nitride traps in MONOS Flash Memory  

Yang, Seung-Dong (Department of Electronics Engineering, Chungnam National University)
Yun, Ho-Jin (Department of Electronics Engineering, Chungnam National University)
Kim, Yu-mi (Department of Electronics Engineering, Chungnam National University)
Kim, Jin-Seob (Department of Electronics Engineering, Chungnam National University)
Eom, Ki-Yun (Department of Electronics Engineering, Chungnam National University)
Chea, Seong-Won (Department of Electronics Engineering, Chungnam National University)
Lee, Hi-Deok (Department of Electronics Engineering, Chungnam National University)
Lee, Ga-Won (Department of Electronics Engineering, Chungnam National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.52, no.8, 2015 , pp. 59-63 More about this Journal
Abstract
This paper discusses the capacitance-voltage method in Metal-Oxide-Nitride-Oxide-Silicon (MONOS) devices to analyzed the characteristics of the top oxide/nitride, nitride/bottom oxide interface trap distribution. In the CV method, nitride trap density can be calculated based on the program characteristics of the nitride thickness variations. By applying this method, silicon rich nitride device found to have a larger trap density than stoichiometric nitride device. This result is consistent with previous studies. If this comparison analysis can be expected to result in improved reliability of the SONOS flash memory.
Keywords
Nitride/Oxide interface trap; MONOS Flash memory; C-V method; silicon rich nitride;
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