• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.10
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• pp.2209-2216
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• 2011

In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.331-340
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• 2012

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction-double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in reduced area overhead. A detailed implementation using fuse technology is also proposed in this paper.

• Smart Structures and Systems
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• v.5 no.5
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• pp.565-585
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• 2009

Superelastic Shape Memory Alloys (SMAs) are gaining acceptance for use as reinforcing bars in concrete structures. The seismic behaviour of concrete frames reinforced with SMAs is being assessed in this study. Two eight-storey concrete frames, one of which is reinforced with regular steel and the other with SMAs at the plastic hinge regions of beams and regular steel elsewhere, are designed and analyzed using 10 different ground motion records. Both frames are located in the highly seismic region of Western Canada and are designed and detailed according to current seismic design standards. The validation of a finite element (FE) program that was conducted previously at the element level is extended to the structure level in this paper using the results of a shake table test of a three-storey moment resisting steel RC frame. The ten accelerograms that are chosen for analyzing the designed RC frames are scaled based on the spectral ordinate at the fundamental periods of the frames. The behaviour of both frames under scaled seismic excitations is compared in terms of maximum inter-storey drift, top-storey drift, inter-storey residual drift, and residual top-storey drift. The results show that SMA-RC frames are able to recover most of its post-yield deformation, even after a strong earthquake.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.781-792
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• 2016

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures $600{\mu}s$ at 1.1 V and $85^{\circ}C$, enhancing by % over the conventional design approach.

• Smart Structures and Systems
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• v.7 no.5
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• pp.329-348
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• 2011

Large-scale earthquakes pose serious threats to infrastructure causing substantial damage and large residual deformations. Superelastic (SE) Shape-Memory-Alloys (SMAs) are unique alloys with the ability to undergo large deformations, but can recover its original shape upon stress removal. The purpose of this research is to exploit this characteristic of SMAs such that concrete Beam-Column Joints (BCJs) reinforced with SMA bars at the plastic hinge region experience reduced residual deformation at the end of earthquakes. Another objective is to evaluate the seismic performance of SMA Reinforced Concrete BCJs repaired with flowable Structural-Repair-Concrete (SRC). A $\frac{3}{4}$-scale BCJ reinforced with SMA rebars in the plastic-hinge zone was tested under reversed cyclic loading, and subsequently repaired and retested. The joint was selected from an RC building located in the seismic region of western Canada. It was designed and detailed according to the NBCC 2005 and CSA A23.3-04 recommendations. The behaviour under reversed cyclic loading of the original and repaired joints, their load-storey drift, and energy dissipation ability were compared. The results demonstrate that SMA-RC BCJs are able to recover nearly all of their post-yield deformation, requiring a minimum amount of repair, even after a large earthquake, proving to be smart structural elements. It was also shown that the use of SRC to repair damaged BCJs can restore its full capacity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.138-142
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• 2004

This paper presents the improved bum-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved through the bum-in process. Reliability problem is more significant in MCP that includes over two chips in a package, because the failure of one chip (SRAM) has a large influence on the yield and quality of the other chips - Flash Memory, DRAM, etc. Therefore, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level bum-in process using multi cells selection method in addition to the previously used methods. That method is effective in detecting special failure. Finally, with the composition of some kind of methods, we could achieve the high quality of SRAM in Multi Chip Package.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.50-60
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• 1997

Reconfiguration of a memory array using spare rows and columns has been known to be a useful technique to improve the yield. When the numbers of spare rows and scolumns are limited, respectively, the repair problem is known to be NP-complete. In this paper, we propose the reconfiguration algorithm for an array of memory cells using faulty cel clustering, which removes rows and columns algrithm is the simplest reconfiguration method with the time complexity of $O(n^2)$, where n is the number of faulty cells, however the repair rate is very low. Whereas the exhaustive search algorithm has a high repair rate, but the time complexity is $O(2^n)$. The proposed algorithm provides the same repair rate as the exhaustive search algorithm for almost all cases and runs as fast as the greedy method. It has the time complexity of $O(n^3)$ in the worst case. We show that the propsed algorithm provides more efficient solutions than other algorithms using simulations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.374-380
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• 2015

As semiconductor devices are being scaled down, random variation becomes a critical issue, especially in the case of static random access memory (SRAM). Thus, there is an urgent need for statistical methodologies to analyze the impact of random variations on the SRAM. In this paper, we propose a novel sampling method based on the concept of a confidence ellipse. Results show that the proposed method estimates the SRAM margin metrics in high-sigma regimes more efficiently than the standard Monte Carlo (MC) method.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1275-1278
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• 2006

A display panel image data manipulator for SOP or SOG is presented. It is capable of all the shift operations for MPEG decoders, graphic processors and controllers as well as data pack, merging, bit split and reformation operations to improve speed and memory utilization. To alleviate poly-Si low yield, redundancy based fault recovery scheme is introduced utilizing regular structure.