JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

Efficient Use of Unused Spare Columns for Reducing Memory Miscorrections

  • Jung, Ji-Hun (Dept. of Computer Science & Engineering, Hanyang University ERICA Campus) ;
  • Ishaq, Umair (Dept. of Computer Science & Engineering, Hanyang University ERICA Campus) ;
  • Song, Jae-Hoon (TranSono Inc.) ;
  • Park, Sung-Ju (Dept. of Computer Science & Engineering, Hanyang University ERICA Campus)
  • Received : 2011.12.15
  • Published : 2012.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction-double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in reduced area overhead. A detailed implementation using fuse technology is also proposed in this paper.

Keywords

References

  1. U. Schlichtmann, "Tomorrows high-quality SoCs require high-quality embedded memories today". In International Symposium on Quality Electronic Design, Mar., 2002.
  2. J. I. Park, et al, "High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm and Its Folded Architecture," Journal of Semiconductor Technology and Science, pp. 193-202, Vol. 10, No. 3, Sep., 2010. https://doi.org/10.5573/JSTS.2010.10.3.193
  3. R. Hamming, "Error Correcting and Error Detecting Codes", Bell Sys. Tech. Journal, Vol. 29, pp.147-160, Apr., 1950. https://doi.org/10.1002/j.1538-7305.1950.tb00463.x
  4. M. Y. Hsiao, "A Class of Optimal Minimum Oddweight-column SEC-DED codes", IBM Journal of Research and Development, Vol. 14, pp. 395-401, 1970. https://doi.org/10.1147/rd.144.0395
  5. M. Richter, et al, "New Linear SEC-DED Codes with Reduced Triple Error Miscorrection Probability," Proc. of International On-Line Testing Symposium, pp. 37-42, 2008.
  6. I. Kim, et al, "Built In Self Repair for Embedded High Density SRAM," Proc. of International Test Conference, pp. 1112-1119, 1998.
  7. Y. Zorian, et al, "Embedded-Memory Test and Repair: Infrastructure IP for SOC Yield," IEEE Design & Test of Computers, Vol. 20, Issue 3, pp. 58-66, May 2003. https://doi.org/10.1109/MDT.2003.1198687
  8. W. Jeong, et al, "An Advanced BIRA for Memories with and Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer," IEEE Transactions on Computer Aided-Design, Vol. 29, No. 12, pp. 2014-2026, Dec. 2010 https://doi.org/10.1109/TCAD.2010.2062830
  9. R. Datta, et al, "Exploiting Unused Spare Columns to Improve Memory ECC," VLSI Test Symposium, 27th IEEE, pp. 47-52, 2009.
  10. W. Peterson, et al, Error Correcting Codes, MIT Press, Cambridge, MA, 1972.
  11. D. K. Pradhan, Fault-Tolerant Computer System Design, Prentice Hall, Upper Saddle River, NJ, 1996.
  12. Y. K. Kim, et al, "Redundancy fuse control circuit and semiconductor memory device having the same and redundancy process method," U. S. Patent 7,184,331, Oct. 27, 2005.
  13. S. H. Kang, "Redundancy circuit in semiconductor memory device," U.S. Patent 7,257,037, Nov. 2, 2006.