• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.92-100
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• 2009

In this paper, we analyze the hardware architecture of Low Density Parity Check (LDPC) decoder using Log Likelihood Ration-Belief Propagation (LLR-BP) decoding algorithm. Various design issues that affect the decoding performance and the hardware complexity are discussed and the tradeoffs between the hardware complexity and the performance are analyzed. The message data for passing error probability is quantized to 7 bits and among them the fractional part is 4 bits. To maintain the decoding performance, the integer and fractional parts for the intrinsic information is 2 bits and 4 bits respectively. We discuss the alternate implementation of $\Psi$(x) function using piecewise linear approximation. Also, we improve the hardware complexity and the decoding time by applying overlapped scheduling.

• Journal of Communications and Networks
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• v.17 no.4
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• pp.339-345
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• 2015

In this paper, we present an iterative reliability-based modified majority-logic decoding algorithm for two classes of structured low-density parity-check codes. Different from the conventional modified one-step majority-logic decoding algorithms, we design a turbo-like iterative strategy to recover the performance degradation caused by the simply flipping operation. The main computational loads of the presented algorithm include only binary logic and integer operations, resulting in low decoding complexity. Furthermore, by introducing the iterative set, a very small proportion (less than 6%) of variable nodes are involved in the reliability updating process, which can further reduce the computational complexity. Simulation results show that, combined with the factor correction technique and a well-designed non-uniform quantization scheme, the presented algorithm can achieve a significant performance improvement and a fast decoding speed, even with very small quantization levels (3-4 bits resolution). The presented algorithm provides a candidate for trade-offs between performance and complexity.

• Journal of Communications and Networks
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• v.5 no.2
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• pp.174-183
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• 2003

Space-Time (ST) codes are known to provide high transmission rates, diversity and coding gains. In this paper, a tight upper bound on the error probability of ST codes over rapid fading channels is presented. Moreover, ST codes suitable for rapid fading channels are presented. These codes are designed using the QPSK and 16-QAM signal constellations. The proposed codes are based on two different encoding schemes. The first scheme uses a single trellis encoder, whereas the second scheme uses the I-Q encoding technique. Code design is achieved via partitioning the signal space such that the design criteria are maximized. As a solution for the decoding problem of I-Q ST codes, the paper introduces a low-complexity decoding algorithm. Results show that the I-Q ST codes using the proposed decoding algorithm outperform singleencoder ST codes with equal complexity. The proposed codes are tested over fading channels with different interleaving conditions, where it is shown that the new codes are robust under such imperfect interleaving conditions.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• ETRI Journal
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• v.43 no.2
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• pp.197-208
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• 2021

Single-carrier frequency division multiple access (SC-FDMA) is currently being used in long-term evolution uplink communications owing to its low peak-to-average power ratio (PAPR). This study proposes a new transceiver design for an SC-FDMA system based on Walsh-Hadamard transform (WHT). The proposed WHT-based SC-FDMA system has low-PAPR and better bit-error rate (BER) performance compared with the conventional SC-FDMA system. The WHT-based SC-FDMA transmitter has the same complexity as that of discrete Fourier transform (DFT)-based transmitter, while the receiver's complexity is higher than that of the DFT-based receiver. The exponential companding technique is used to reduce its PAPR without degrading its BER. Moreover, the performances of different ordered WHT systems have been studied in additive white Gaussian noise and multipath fading environments. The proposed system has been verified experimentally by considering a real-time channel with the help of wireless open-access research platform hardware. The supremacy of the proposed transceiver is demonstrated based on simulated and experimental results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.15-23
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• 2009

This paper presents a novel high-speed, low-complexity flexible 128/64-point $radix-2^4$ FFT/IFFT processor for the applications in high-throughput MIMO-OFDM systems. The high radix multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. The proposed processor not only supports the operation of FFT/IFFT in 128-point and 64-point but can also provide a high data processing rate by using a four-parallel data-path scheme. Furthermore, the proposed design has a less hardware complexity compared with traditional 128/64-point FFT/IFFT processors. Our proposed processor has a high throughput rate of up to 560Msample/s at 140MHz while requiring much smaller hardware expenditure satisfying IEEE 802.11n standard requirements.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.145-151
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• 2003

This study focuses on the hardware implementation of fast and low-complexity multiplier over GF(2$^{m}$ ). Finite field multiplication can be realized in two steps: polynomial multiplication and modular reduction using the irreducible polynomial and we will treat both operation, separately. Polynomial multiplicative operation in this Paper is based on the Permestzi's algorithm, and irreducible polynomial is defined AOP. The realization of the proposed GF(2$^{m}$ ) multipleker-based multiplier scheme is compared to existing multiplier designs in terms of circuit complexity and operation delay time. Proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.2
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• pp.117-125
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• 2003

In this paper, we propose a new code acquisition architecture having the features of low complexity and high speed for the MC-CDMA system. The newly designed searching finger has function of the searcher as well as the finger. The searching finger tests the PN code Phase as the searcher during the initial acquisition, and as the finger after the initial acquisition. The proposed system has reduced the average acquisition time of the PN codes to $T_{acq}$/19 in the 20MHz MC-CDMA system with 75% reduction of H/W complexity.y.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.3
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• pp.85-90
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• 2003

This paper proposes a modular multiplier based on LFSR (Linear Feedback Shift Register) architecture with efficient area complexity over GF(2/sup m/). At first, we examine the modular exponentiation algorithm and propose it's architecture, which is basic module for public-key cryptosystems. Furthermore, this paper proposes on efficient modular multiplier as a basic architecture for the modular exponentiation. The multiplier uses AOP (All One Polynomial) as an irreducible polynomial, which has the properties of all coefficients with '1 ' and has a more efficient hardware complexity compared to existing architectures.

• Proceedings of the KIEE Conference
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• 2004.05a
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• pp.56-58
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• 2004

In this paper, we propose an adaptive beamforming algorithm for array antenna. The proposed beamforming algorithm is based on EDS (Euclidean Direction Search) algorithm. Generally LMS algorithm has a much slower rate of convergence, but its low computational complexity and robustness make it a representative method of adaptive beamforming. Although the RLS algorithm is known for its fast convergence to the optimal Wiener solution, it still suffers from high computational complexity and poor performance. The proposed EDS algorithm has a rapid convergence better than LMS algorithm, and has a computational more simple complexity than RLS algorithm. In this paper we compared the efficiency of the EDS algorithm with a standard LMS algorithm.