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Performance Analysis on Various Design Issues of Quasi-Cyclic Low Density Parity Check Decoder  

Chung, Su-Kyung (Department of Information, Communication and Electronic Engineering, The Catholic University of Korea)
Park, Tae-Geun (Department of Information, Communication and Electronic Engineering, The Catholic University of Korea)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.11, 2009 , pp. 92-100 More about this Journal
Abstract
In this paper, we analyze the hardware architecture of Low Density Parity Check (LDPC) decoder using Log Likelihood Ration-Belief Propagation (LLR-BP) decoding algorithm. Various design issues that affect the decoding performance and the hardware complexity are discussed and the tradeoffs between the hardware complexity and the performance are analyzed. The message data for passing error probability is quantized to 7 bits and among them the fractional part is 4 bits. To maintain the decoding performance, the integer and fractional parts for the intrinsic information is 2 bits and 4 bits respectively. We discuss the alternate implementation of $\Psi$(x) function using piecewise linear approximation. Also, we improve the hardware complexity and the decoding time by applying overlapped scheduling.
Keywords
Low density parity check(LDPC) codes; quasi-cyclic LDPC; Belief Propagation; fixed-length analysis;
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