Browse > Article

The Design of $GF(2^m)$ Multiplier using Multiplexer and AOP  

변기영 (가톨릭대학교 정보통신전자공학부)
황종학 (국민체육진흥공단 체육과학연구원)
김흥수 (인하대학교 전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.40, no.3, 2003 , pp. 145-151 More about this Journal
Abstract
This study focuses on the hardware implementation of fast and low-complexity multiplier over GF(2$^{m}$ ). Finite field multiplication can be realized in two steps: polynomial multiplication and modular reduction using the irreducible polynomial and we will treat both operation, separately. Polynomial multiplicative operation in this Paper is based on the Permestzi's algorithm, and irreducible polynomial is defined AOP. The realization of the proposed GF(2$^{m}$ ) multipleker-based multiplier scheme is compared to existing multiplier designs in terms of circuit complexity and operation delay time. Proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.
Keywords
finite field; multiplexer; all one polynomial; standard basis; multiplier;
Citations & Related Records
연도 인용수 순위
  • Reference
1 C.S.Yeh, I.S.Reed, and T.K.Trung, 'Systolic Multipliers for Finite Field GF$(2^m)$,' IEEE Trans. Computer, vol. C-33, pp. 357-360, April 1984   DOI   ScienceOn
2 T.ltoh, and S.Tsujii, 'Structure of Parallel Multipliers for a Class of Fields GF$(2^m)$,' Information and Computation, vol. 83, pp. 21-40, 1989   DOI
3 S.Lin, Error Control Coding, Prentice-Hall, Inc. New Jersey, 1983
4 이만영, BCH부호와 Reed-Solomon부호, 민음사, 1990
5 B.A.Laws and C.K.Rushford, 'A Cellular-Array Multiplier for GF$(2^m)$ IEEE Trans. Computer, vol. C-20, no. 12, pp. 1573-1578, Dec. 1971   DOI   ScienceOn
6 J.Omura and J.Massey, 'Computational Method and Apparatus for Finite Fields,' U.S. Patent no. 4,587,627, May 1986
7 C.C.Wang, T.K.Trung, H.M.Shao, L.J.Deutsch, J.K. Omura, and I.S.Reed, 'VLSI Architecture for Computing Multiplications and Inverses in GF$(2^m)$,' IEEE Trans. Comp., vol.C-34, pp. 709-717, Aug. 1985   DOI   ScienceOn
8 B.Sunar, and C.K.Koc, 'Mastrovito Multiplier for All Trinomials,' IEEE Trans. Computers, vol. 48, no. 5, pp. 522-527, May 1999   DOI   ScienceOn
9 A.Haibutogullari, and C.K.Koc, 'Mastrovito Multiplier for General Irreducible Polynomials,' IEEE Trans. Computers, vol. 49, no. 5, pp. 503-518, May 2000   DOI   ScienceOn
10 T.Zhang, and K.K.Parhi, 'Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials,' IEEE Trans. Computers, vol. 50, no. 7, pp. 734-748, July 2001   DOI   ScienceOn
11 C.K.Koc, and B.Sunar, 'Low-Complexity Bit Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields,' IEEE Trans. Computer, vol. 47, no.3, pp. 353-283. March 1998   DOI   ScienceOn
12 C.Y.Lee, E.H.Lu, and J.Y.Lee, 'Bit-Parallel Systolic Multipliers for GF$(2^m)$ Fields Defined by All-One and Equally Spaced Polynomials,' IEEE Trans. Computers, vol. m, No.5, pp. 385-393, May 2001   DOI   ScienceOn
13 B. Parhami, Computer Arithmetic- Algorithms and Hardware Designs, Oxford University Press, Inc., 2000
14 K.Z.Pekmestzi, 'Multiplexer-Based Array Multipliers,' IEEE Trans. Computer, vol. 48, no.1, pp. 15-23. Jan. 1999   DOI   ScienceOn
15 S.M.Kang, and Y.Leblebici, CMOS Digital Integrated Circuits-Analysis and Design, McGraw-Hill, 1999
16 R.J.Baker, H.W.Li, and D.E.Boyce, CMOS-Circuit Design, Layout, and Simulation, IEEE Press, 1998