• 제목/요약/키워드: low input voltage

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A 0.18-μm CMOS Baseband Circuits for the IEEE 802.15.4g MR-OFDM SUN Standard (IEEE 802.15.4g MR-OFDM SUN 표준을 지원하는 0.18-μm CMOS 기저대역 회로 설계에 관한 연구)

  • Bae, Jun-Woo;Kim, Chang-Wan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.3
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    • pp.685-690
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    • 2013
  • This paper has proposed a multi-channel and wide gain-range baseband circuit blocks for the IEEE 802.15.4g MR-OFDM SUN systems. The proposed baseband circuit blocks consist of two negative-feedback VGAs, an active-RC 5th-order chebyshev low-pass-filter, and a DC-offset cancellation circuit. The proposed baseband circuit blocks provide 1 dB cut-off frequencies of 100 kHz, 200 kHz, 400 kHz, and 600 kHz respectively, and achieve a wide gain-range of +7 dB~+84 dB with 1 dB step. In addition, a DC-offset cancellation circuit has been adopted to mitigate DC-offset problems in direct-conversion receiver. Simulation results show a maximum input differential voltage of $1.5V_{pp}$ and noise figure of 42 dB and 37.6 dB at 5 kHz and 500 kHz, respectively. The proposed I-and Q-path baseband circuits have been implemented in $0.18-{\mu}m$ CMOS technology and consume 17 mW from a 1.8 V supply voltage.

A Study on the Discharge Guide Technology by infrared Laser Applied to Discharge Processing Devices (적외선 레이저에 의한 방전 유도 기술의 방전 가공 장치에의 적용 연구)

  • 조정수;이동훈;남경훈
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.13 no.1
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    • pp.1-8
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    • 1999
  • In recent years, concern has been raised about the technique of controlling electrical breakdown by using laser in many fields. Especially, laser has attracted much attention in the Electro-Discharge Machining(EDM) because of its many rrents. 1berefore, this research has been perfonred to obtain fundarrental data for the discharge guide technology by a pulsed Nd:YAG laser which can be awJied to discharge processing machining. 1be experilnnts of laser-guided de discharge have been carried out at low air pressure ranging from 0.2 to 20 torr. The minimum laser-guided de discharge voltage $V_{G.min}$ at the given pressures P and distances d between an anode and a cathode was rreasured It is found that $V_{G.min}$ is much lower than the natural discharge voltage $V_{ND}$, and the values of VGrrin and $V_{ND}$ as a function of P.d has a similar tendency. The laser output energy $E_{out}$ decreases with input pulse duration $t_p$ increasing, and the rrore the value of $t_p$ increases, the higher that of V$V_{G.min}$ is obtained because the number of photons N decreases with $t_p$ increasing. In addition, the laser-guided de discharge range and the discharge guide characteristics as laser outpIt $E_{out}$ was investigated.igated.

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Analyzing of CDTA using a New Small Signal Equivalent Circuit and Application of LP Filters (새로운 소신호 등가회로를 활용한 CDTA의 해석 및 저역통과 필터설계)

  • Bang, Junho;Song, Je-Ho;Lee, Woo-Choun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.15 no.12
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    • pp.7287-7291
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    • 2014
  • A CDTA (current differencing transconductance amplifier) is an active building block for current mode analog signal processing with the advantages of high linearity and a wide frequency bandwidth. In addition, it can generate a stable voltage because all the differencing input current flows to the grounded devices. In this paper, a new small signal equivalent circuit is proposed to analyze a CDTA. The proposed small signal equivalent circuit provides greater precision in analyzing the magnitude and frequency response than its previous counterparts because it considers the parasitic components of the input, internal and output terminal. In addition, observations of the changes made in various devices, such as the resistor (Rz) confirmed that those devices heavily influence the characteristics of CDTA. The designed parameters of the proposed small signal equivalent circuit of the CDTA provides convenience and accuracy in the further design of analog integrated circuits. For verification purposes, a 2.5 MHz low pass filter was designed on the HSPICE simulation program using the proposed small signal equivalent circuit of CDTA.

A 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for High-Quality Video Systems (고화질 영상 시스템 응용을 위한 12비트 130MS/s 108mW $1.8mm^2$ 0.18um CMOS A/D 변환기)

  • Han, Jae-Yeol;Kim, Young-Ju;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.3
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    • pp.77-85
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    • 2008
  • This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

A Study on the Fabrication of K-band Local Oscillator Used Frequency Doubler Techniques (주파수 체배 기법을 이용한 K-대역 국부발진기 구현에 관한 연구)

  • 김장구;박창현;최병하
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.10
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    • pp.109-117
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    • 2004
  • In this paper, a K-band local oscillator composed of a VCDRO(Voltage Controlled Dielectric Resonator Oscillator), GaAs MESFET, and Reflector type frequency doubler has been designed and fabricated. TO obtain a good phase noise performance of a VCDRO, a active device was selected with a low noise figure and a low flicker noise MESFET and a dielectric resonator was used for selecting stable and high oscillation frequency. Especially, to have a higher conversion gain than a conventional doubler as well as a good harmonic suppression performance with circuit size reduced a doubler structure was employed as the Reflector type composed of a reflector and a open stub of quarter wave length for rejecting the unwanted harmonics. The measured results of fabricated oscillator show that the output power was 5.8 dBm at center frequency 12.05 GHz and harmonic suppression -37.98 dBc, Phase noise -114 dBc at 100 KHz offset frequency, respectively, and measured results show of fabricated frequency doubler, the output power at 5.8 dBm of input power is 1.755 dBm conversion gain 1.482 dB, harmonic suppression -33.09 dBc, phase noise -98.23 dBc at 100 KHz offset frequency, respectively. This oscillator could be available to a local oscillator in K-band which used frequency doubler techniques.

Third order Sigma-Delta Modulator with Delayed Feed-forward Path for Low-power Operation (저전력 동작을 위한 지연된 피드-포워드 경로를 갖는 3차 시그마-델타 변조기)

  • Lee, Minwoong;Lee, Jongyeol
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.10
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    • pp.57-63
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    • 2014
  • This paper proposes an architecture of $3^{rd}$ order SDM(Sigma-Delta Modulator) with delayed feed-forward path in order to reduce the power consumption and area. The proposed SDM improve the architecture of conventional $3^{rd}$ order SDM which consists of two integrators. The proposed architecture can increase the coefficient values of first stage doubly by inserting the delayed feed-forward path. Accordingly, compared with the conventional architecture, the capacitor value($C_I$) of first integrator is reduced by half. Thus, because the load capacitance of first integrator became the half of original value, the output current of first op-amp is reduced as 51% and the capacitance area of first integrator is reduced as 48%. Therefore, the proposed method can optimize the power and the area. The proposed architecture in this paper is simulated under conditions which are supply voltage of 1.8V, input signal 1Vpp/1KHz, signal bandwidth of 24KHz and sampling frequency of 2.8224MHz in the 0.18um CMOS process. The simulation results are SNR(Signal to Noise Ratio) of 88.9dB and ENOB(Effective Number of Bits) of 14-bits. The total power consumption of the proposed SDM is $180{\mu}W$.

A Design of the New Three-Line Balun (새로운 3-라인 발룬 설계)

  • 이병화;박동석;박상수
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.7
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    • pp.750-755
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    • 2003
  • This paper proposes a new three-line balun. The equivalent circuit of the proposed three-line balun is presented, and impedance matrix[Z]of the equivalent circuit is derived from the relationship between the current and voltage at each port. The design equation for a given set of balun impedance at input and output ports is presented using[S]parameters, which is transferred fom impedance matrix,[Z]. To demonstrate the feasibility and validity of design equation, multi-layer ceramic(MLC) chip balun operated in the 2.4 GHz ISM band frequency is designed and fabricated by the use of the low temperature co-fired ceramic(LTCC) technology. By employing both the proposed new three-line balun equivalent circuit and multi-layer configuration provided by LTCC technology, the 2012 size MLC balun is realized. Measured results of the multi-layer LTCC three-line balun match well with the full-wave electromagnetic simulation results, and measured in band-phase and amplitude balances over a wide bandwidth are excellent. This proposed balun is very easily applicable to multi-layer structure using LTCC as shown in the paper, and also can be realized with microstrip lines on PCB. This distinctive performance is very favorable for wireless communication systems such as wireless LAN(Local Area Network) and Bluetooth applications.

A Re-configurable 0.8V 10b 60MS/s 19.2mW 0.13um CMOS ADC Operating down to 0.5V (0.5V까지 재구성 가능한 0.8V 10비트 60MS/s 19.2mW 0.13um CMOS A/D 변환기)

  • Lee, Se-Won;Yoo, Si-Wook;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.3
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    • pp.60-68
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    • 2008
  • This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

The Design and Fabrication of Conversion Layer for Application of Direct-Detection Type Flat Panel Detector (직접 검출형 평판 검출기 적용을 위한 변환층 설계 및 제작)

  • Noh, Si-Cheol;Kang, Sang-Sik;Jung, Bong-Jae;Choi, Il-Hong;Cho, Chang-Hoon;Heo, Ye-Ji;Yoon, Ju-Seon;Park, Ji-Koon
    • Journal of the Korean Society of Radiology
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    • v.6 no.1
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    • pp.73-77
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    • 2012
  • Recently, Interest to the photoconductor, which is used to flat form X-ray detector such as a-Se, $HgI_2$, PbO, CdTe, $PbI_2$ etc. is increasing. In this study, the film layer by using the photoconductive material with particle sedimentation was fabricated and evaluated. The quantization efficiency of the continuous X-ray with the 70 kVp energy bandwidth was analyzed by using the Monte Carlo simulation. With the results, the thickness of film with 64 % quantization efficiency was 180 ${\mu}m$ which is similar to the efficiency of 500 ${\mu}m$ a-Se film. And $HIg_2$ film has the high quantization efficiency of 74 % on 240 ${\mu}m$ thickness. The electrical characteristics of the 239 ${\mu}m$ $Hgl_2$ films produced by particle sedimentation were shown as very low dark current(under 10 $pA/mm^2$), and high sensitivity(19.8 mC/mR-sec) with 1 $V/{\mu}m$ input voltage. The SNR, which is influence to the contrast of X-ray image, was shown highly as 3,125 in low driving voltage on 0.8 $V/{\mu}m$. With the results of this study, the development of the low-cost, high-performance image detector with film could be possible by replacing the film produced by particle sedimentation instead to a-Se detector.

The Usefulness of Bone Scan in Electric Burns (전기화상에서 골스캔의 유용성)

  • Kim, Tae-Hyung;So, Yong-Seon;Kweon, Ki-Hyeon;Han, Sang-Woong;Kim, Seok-Hwan;Kim, Jong-Soon;Han, Seung-Soo
    • The Korean Journal of Nuclear Medicine
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    • v.30 no.1
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    • pp.130-138
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    • 1996
  • Bone scan is known to be an effective tool for observing the state of soft tissues and bones of electric burn patients. It is also used for observing the progress of patients after debridement or skin graft as well as deforming to amputate specific body parts. To evaluate bone scan's role in electric burn, we analyzed bone scan 37 patients with electric burn. Among the 37 patients, 8 of 37 were injured in low voltage and 29 of them in high voltage. 27 patients received the electrical input through the hand, 6 through the scalp, 2 through the shoulder, 1 through the left chest wall and 1 through the left inguinal area. Among 29 patients received high voltage, 22 patients had the electrical output through the foot, 3 through the hand, 2 through the shoulder, 1 through the buttock and 1 through the left chest wall. Bone scans revealed cellulitis in 37 patients with 47 sites, osteomyelitis in 15 patients with 15 sites & bone defects in 4 patients with 4 sites. In 4 patients with skin graft or skin flap, follow up bone scan showed improvements of bony uptake in preoperatively bony defect area and all of them were healed without complication. There were 2 cases in which uptake increased in the myocardium, 1 in the liver and 6 in the kidney, however, serum calcium level, EKG, cardiac enzyme, liver and renal function tests were normal. In conclusion, bone scans are helpful in the assessment of injury sites after electrical insult and in differential diagnosis of cellulitis and osteomyelitis. It is also useful tool of assessment after skin graft or skin flap, however, it should be further evaluated about internal organ damage.

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