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A Re-configurable 0.8V 10b 60MS/s 19.2mW 0.13um CMOS ADC Operating down to 0.5V  

Lee, Se-Won (Dept. of Electronic Engineering, Sogang University)
Yoo, Si-Wook (CIS Division, Hynix Semiconductor)
Lee, Seung-Hoon (Dept. of Electronic Engineering, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.3, 2008 , pp. 60-68 More about this Journal
Abstract
This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.
Keywords
ADC; CMOS;
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