• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.486-489
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• 2010

This paper describes a layered LDPC decoder which supports block length of 1,944 bits and code rate 1/2 for IEEE 802.11n WLAN standard. To reduce the hardware complexity, the min-sum algorithm and layered architecture is adopted. A novel memory reduction technique suitable for min-sum algorithm reduces memory size by 75% compared with conventional method. The designed processor has 200,400 gates and 19,400 bits memory, and it is verified by FPGA implementation. The estimated throughput is about 200 Mbps at 120 MHz clock by using Xilinx Virtex-4 FPGA device.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.1
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• pp.1-14
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• 2024

Time-series forecasting is extensively used in the actual world. Recent research has shown that Transformers with a self-attention mechanism at their core exhibit better performance when dealing with such problems. However, most of the existing Transformer models used for time series prediction use the traditional encoder-decoder architecture, which is complex and leads to low model processing efficiency, thus limiting the ability to mine deep time dependencies by increasing model depth. Secondly, the secondary computational complexity of the self-attention mechanism also increases computational overhead and reduces processing efficiency. To address these issues, the paper designs an efficient multi-layer attention-based time-series forecasting model. This model has the following characteristics: (i) It abandons the traditional encoder-decoder based Transformer architecture and constructs a time series prediction model based on multi-layer attention mechanism, improving the model's ability to mine deep time dependencies. (ii) A cross attention module based on cross attention mechanism was designed to enhance information exchange between historical and predictive sequences. (iii) Applying a recently proposed sparse attention mechanism to our model reduces computational overhead and improves processing efficiency. Experiments on multiple datasets have shown that our model can significantly increase the performance of current advanced Transformer methods in time series forecasting, including LogTrans, Reformer, and Informer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.50-57
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and compared with the previous results.

• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.498-512
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• 2010

Intra coding is an indispensable coding tool since it can provide random accessibility as well as error resiliency. However, it is the problem that intra coding has relatively low coding efficiency compared with inter coding in the area of video coding. Even though H.264/AVC has significantly improved the intra coding performance compared with previous video standards, H.264/AVC encoder complexity is significantly increased, which is not suitable for low bit rate interactive services. In this paper, a Voting-based Intra Mode Bit Skip (V-IMBS) scheme is proposed to improve coding efficiency as well as to reduce encoding time complexity using decoder-side prediction. In case that the decoder can determine the same prediction mode as what is chosen by the encoder, the encoder does not send that intra prediction mode; otherwise, the conventional H.264/AVC intra coding is performed. Simulation results reveal a performance increase up to 4.44% overall rate savings and 0.24 dB in peak signal-to-noise ratio while the frame encoding speed of proposed method is about 42.8% better than that of H.264/AVC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.47-52
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• 2009

H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation and management of the reference pixels. The reference pixels read from external memory using efficient memory management for data reuse is necessary along with the high performance interpolators. We propose the architecture of a motion compensation unit for H.264 decoders. It is composed of 2-dimensional circular register files, a motion vector predictor and high performance interpolators with low complexity. The 2-dimensional circular register files reuse reference pixel data as much as possible, and feed reference pixel data to interpolators without any latency and complex logic circuits. We design a motion compensation unit and a intra-prediction unit and integrate them into a prediction unit and verify the operation and the performance.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.5
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• pp.151-161
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• 2009

Audio Video Standard (AVS) is the audio and video compression standard that was developed for domestic video applications in China. AVS employs low complexity tools to minimize degradation of RD performance of the state-the-art video codec, H.264/AVC. The AVS video codec consists of $8{\times}8$ block prediction and the same size transform to improve compression efficiency for VGA and higher resolution sequences. Currently, the AVS has been adopted more and more for IPTV services and mobile applications in China. So, many consumer electronics companies and multimedia-related laboratories have been developing applications and chips for the AVS. In this paper, we implemented the AVS video decoder and optimize it on TI's Davinci EVM DSP board. For improving the decoding speed and clocks, we removed unnecessary memory operations and we also used high-speed VLD algorithm, linear assembly, intrinsic functions and so forth. Test results show that decoding speed of the optimized decoder is $5{\sim}7$ times faster than that of the reference software (RM 5.2J).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• The Journal of the Acoustical Society of Korea
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• v.30 no.4
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• pp.190-196
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• 2011

Bandwidth extension is a technique to improve speech quality and intelligibility, extending from 300-3400 Hz narrowband speech to 50-7000 Hz wideband speech. This paper designs an artificial bandwidth extension (ABE) module embedded in the AMR (adaptive multi-rate) decoder, reducing LPC/LSP analysis and algorithm delay of the ABE module. We also introduce a fast search codebook mapping method for ABE, and design a low power BWE technique based on the AMR decoder. The proposed ABE method reduces the computational complexity and the algorithm delay, respectively, by 28 % and 20 msec, compared to the traditional DTE (decode then extend) method. We also introduce a weighted classified codebook mapping method for constructing the spectral envelope of the wideband speech signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2C
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• pp.262-271
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• 2004

There are channel errors when video data are transmitted between encoder and decoder. These channel errors would make decoded image incorrect, so it is very important to detect and recover channel errors. This paper proposes a method of error detection and recovery by hiding specific information into video bitstream using fragile watermark and checking it later. The proposed method requires no additional bits into compressed bitstream since it embeds a user-specific data pattern in the least significant bits of LEVELs in VLC codewords. The decoder can extract the information to check whether the received bitstream has an error or not. We also propose to use this method to embed essential data such as motion vectors that can be used for error recovery. The proposed method can detect corrupted MBs that usually escape the conventional syntax-based error detection scheme. This proposed method is quite simple and of low complexity. So the method can be applied to multimedia communication system in low bitrate wireless channel.

• Journal of Advanced Navigation Technology
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• v.10 no.4
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• pp.371-376
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• 2006

The initial radius of sphere decoder has great effect on the bit error rate performance and computational complexity. Until now, it has been determined either by considering the statistical property of channel or by using of MMSE solution. The initial radius obtained by using statistical property of channel includes the lattice point corresponding to the transmit signal vector with very high probability. The method using MMSE solution first calculates out the MMSE solution of the received signal, then maps the hard decision of this solution into the received signal space, and finally the distance between the mapped point and the received signal is selected as the initial radius of the sphere decoding. In this paper, we derive a simple equation for initial radius selection which uses statistical property of channel and compare it with the method using MMSE solution. To compare two methods we define new metric 'Tightness'. Through the simulation, we observe that in low and moderate SNR region, the method using MMSE solution provides more complexity reduction for decoding while in high SNR region, the method using channel statistics is better.