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Design of Prediction Unit for H.264 decoder  

Lee, Chan-Ho (School of Electronic Engr., Soongsil University)
Publication Information
Abstract
H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation and management of the reference pixels. The reference pixels read from external memory using efficient memory management for data reuse is necessary along with the high performance interpolators. We propose the architecture of a motion compensation unit for H.264 decoders. It is composed of 2-dimensional circular register files, a motion vector predictor and high performance interpolators with low complexity. The 2-dimensional circular register files reuse reference pixel data as much as possible, and feed reference pixel data to interpolators without any latency and complex logic circuits. We design a motion compensation unit and a intra-prediction unit and integrate them into a prediction unit and verify the operation and the performance.
Keywords
H.264 Decoder; Motion Compensation; Interpolator; circular register files;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 Mythri Alle et al, 'High performance VLSI implementation for H.264 InterlIntra prediction', Proceedings of IEEE International Conference on Comsumer Electonics, pp.l-2, Jan. 2007
2 Joint Video Team, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification. ITU-T Rec. H.264 and ISO!IEC 14400-10 AVC, May 2003
3 Wen-Nung Lie, Han-Ching Yeh, Lin, T.c.-I., Chien-Fa Chen, 'Hardware-efficient computing architecture for motion compensation interpolation in H.264 video coding', Proceedings of IEEE International Symposium on Circuits and Systems, Vol. 3, pp. 2136-2139, May 23-26, 2005
4 이찬호, 'H.264 복호기를 위한 스케일러블 인트라예측기 구조설계,' 전자공학회 논문지, 제45권 SD편 제11호, pp.77-81, 2008.11
5 Jaemoon Kiln, Woong Hwangbo, Chong-Min Kyung, 'A Novel Bus Interface and Motion Compensation Architecture for H.264/ A VC with Reduced Memory Access,' 16회 한국반도체학술대회, 대전, 2009.2.20
6 Chuan-Yung Tsai, Tung-Chien Chen, To-Wei Chen, Liang-Gee Chen, 'Bandwidth Optimized Motion Compensation Hardware Design for H.264/ AVC lIDTV Deccxler' Proceedings of 48th Midwest Symposium on Circuits and Systems, Vol. 2, pp. 1199-1202, Aug. 7-10, 2005
7 Ronggang Wang, Mo Li, Jintao Li, Yongdong Zhang, "High throughput and low memory access sub-pixel interpolation architecture for H.264/ A VC lIDTV deccxler", IEEE Transactions on Consumer Electronics, Vol. 51, pp. 1006-1013, Aug. 2005   DOI   ScienceOn
8 Yonghoon Yu, Chanho Lee, 'Design of Low-Complexity Interpolator for Motion Compensation in H.264 deccxler' Proceedings of International Conference on Circuits/Systems Computers and Communications, pp.225-228, Jul. 2008
9 Sheng-Zen Wang, Ting-An Lin, Tsu-Ming Liu, Chen-Yi Lee, 'A new motion compensation design for H.264/ A VC deccxler' IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 4558-4561, May 23-26, 2005