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Design of an Efficient LDPC Codec for Hardware Implementation  

Lee Chan-Ho (School of Electronic Engr., Soongsil University)
Park Jae-Geun (Dept. of Electronic Engr., Soongsil University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.7, 2006 , pp. 50-57 More about this Journal
Abstract
Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and compared with the previous results.
Keywords
Low density parity check (LDPC); semi-random; Hybrid H-matrix; partly parallel structure;
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