• Journal of information and communication convergence engineering
• /
• v.3 no.1
• /
• pp.18-22
• /
• 2005

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.5
• /
• pp.65-70
• /
• 2008

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

• Journal of Navigation and Port Research
• /
• v.31 no.9
• /
• pp.763-769
• /
• 2007

A narrow loop noise bandwidth method is desirable to reduce the error of raw measurements due to the thermal noise. However, it degrades the performance of GPS initial synchronization such as mean acquisition time. And it restricts the loop noise bandwidth to a fixed value determined by the lower bound of the allowable range of carrier-to-noise power ratio, so that it is difficult to optimally track GPS signal. In order to make up for the weak points of the fixed-type narrow loop noise bandwidth method and simultaneously minimize the error of code and carrier measurements, this paper proposes a stepwise-type adaptive bandwidth algorithm for DGPS reference receivers. In this paper, it is shown that the proposed adaptive bandwidth algorithm can provide more accurate measurements than those of the fixed-type narrow loop noise bandwidth method, in view of analyzing the simulation results between two signal tracking algorithms. This paper also carries out sensitivity analysis of the proposed adaptive bandwidth algorithm due to the estimation uncertainty of carrier-to-noise power ratio. Finally the analysis results are verified by the experiment using GPS simulator.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.3
• /
• pp.582-586
• /
• 2005

This paper presents a new structure of Phase Locked Loop(PLL) which changes its loop bandwidth according to the locking status. The proposed PLL consists of a conventional PLL and, Locking Status Indicator(LSI). The LSI decides the operating bandwidth of loop filler. When the PLL becomes out of lock, the PLL increases the loop bandwidth and achieves fast locking. When the PLL becomes in-lock, this PLL decreases the loop bandwidth and minimizes phase noise output. The PLL can achieve fast locking and low phase noise output at the same time. Proposed PLL's locking time is less than $40{\mu}s$ and spur is 76.1dBc. It is simulated by HSPICE in a Hynix CMOS $0.35{\mu}m$ Process.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.3
• /
• pp.141-144
• /
• 2015

A broadband radio frequency synthesizer for multi-band, multi-standard mobile DTV tuners is proposed, it's loop bandwidth can be calibrated to optimize integrated phase noise performance without the problem of phase noise peaking. For this purpose, we proposed a new third-order scalable loop filter and a scalable charge pump circuit to minimize the variation in phase margin during calibration. The prototype phase-lock loop is fabricated in 180nm complementary metal-oxide semiconductor shows that it effectively prevents phase noise peaking from growing while the loop bandwidth increases by up to three times.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.12A
• /
• pp.983-990
• /
• 2003

In this paper, a noncoherent code tracking loop is designed for 3GPP MODEM and its performance is analyzed in terms of steady-state jitter variance and transient response characteristics. An analytical closed-form formula for steady-state jitter variance is Int derived for AWGN environments as a general function of a pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth, together with the analysis on the transient response characteristic of a tracking loop. Based on the analysis, the code tracking loop with variable loop bandwidth that is efficient for full digital H/W implementation is designed and its performance is compared with that of the code tracking loop with fixed loop bandwidth, along with the verification by computer simulations.

• International Journal of Control, Automation, and Systems
• /
• v.6 no.6
• /
• pp.948-953
• /
• 2008

In high dynamic situations, the GPS carrier tracking loop requires a wide bandwidth to track a carrier signal because the Doppler frequency changes more rapidly with time. However, a wide bandwidth allows noises within the bandwidth of the tracking loop to pass through the loop filter. As these noises are used in the numerical controlled oscillator(NCO), the carrier tracking loop of a GPS receiver shows a degraded performance in high dynamic situations. To solve this problem, an adaptive two-stage Kalman filter, which offers the NCO a less noisy phase error, can be used. This filter is based on a carrier phase dynamic model and can adapt to an incomplete dynamic model and a quickly changed Doppler frequency. The performance of the proposed tracking loop is verified by several simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.146-153
• /
• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• International Journal of Control, Automation, and Systems
• /
• v.6 no.4
• /
• pp.596-606
• /
• 2008

In this paper, we present a co-design methodology of dynamic optimal network-bandwidth allocation (ONBA) and adaptive control for networked control systems (NCSs) to optimize overall control performance and reduce total network-bandwidth usage. The proposed dynamic co-design strategy integrates adaptive feedback control with real-time scheduling. As part of this co-design methodology, a "closed-loop" ONBA algorithm for NCSs with communication constraints is presented. Network-bandwidth is dynamically assigned to each control loop according to the quality of performance (QoP) information of each control loop. As another part of the co-design methodology, a network quality of service (QoS)-adaptive control design approach is also presented. The idea is based on calculating new control values with reference to the network QoS parameters such as time delays and packet losses measured online. Simulation results show that this co-design approach significantly improves overall control performance and utilizes less bandwidth compared to static strategies.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.4
• /
• pp.568-576
• /
• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.