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A Fast Locking Dual-Loop PLL with Adaptive Bandwidth Scheme  

Song, Youn-Gui (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University)
Choi, Young-Shig (Division of Electronics, Computer and Telecommunication Engineering, Pukyong National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.5, 2008 , pp. 65-70 More about this Journal
Abstract
A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.
Keywords
Phase locked loop(PLL); dual-loop; fast locking; adaptive bandwidth;
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