• Journal of information and communication convergence engineering
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• 제3권1호
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• pp.18-22
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• 2005

This paper presents the analog adaptive phase-locked loop (PLL) architecture with a new adaptive bandwidth controller to reduce locking time and minimize jitter in PLL output for wireless communication. It adaptively controls the loop bandwidth according to the locking status. When the phase error is large, the PLL increases the loop bandwidth and reduces locking time. When the phase error is small, the PLL decreases the loop bandwidth and minimizes output jitters. The adaptive bandwidth control is implemented by controlling charge pump current depending on the locking status. A 1.28-GHz CMOS phase-locked loop with adaptive bandwidth control is designed with 0.35 $mu$m CMOS technology. It is simulated by HSPICE and achieves the primary reference sidebands at the output of the VCO are approximately -80dBc.

• 대한전자공학회논문지SD
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• 제45권5호
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• pp.65-70
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• 2008

본 논문에서는 루프 대역폭을 조절하여 빠른 위상 고정 시간을 갖는 새로운 구조의 이중 루프 위상고정루프를 제안하였다. 위상고정루프가 out-lock 상태일 때는 채널 간격의 1/10보다 더 큰 대역폭을 갖도록 하였으며, in-lock 부근에서는 채널 간격의 1/10 보다 더 작은 좁은 대역폭을 갖도록 하였다. 제안된 위상고정루프는 표준 CMOS $0.35{\mu}m$ 공정으로 HSPICE를 이용하여 설계 하였다. 시뮬레이션 결과 PLL의 대역폭을 200KHz 채널 간격 보다 14배 크게 하여 80MHz의 주파수를 변화시키는데 $50{\mu}s$의 빠른 위상고정 시간을 갖는 것으로 나타났다.

• 한국항해항만학회지
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• 제31권9호
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• pp.763-769
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• 2007

A narrow loop noise bandwidth method is desirable to reduce the error of raw measurements due to the thermal noise. However, it degrades the performance of GPS initial synchronization such as mean acquisition time. And it restricts the loop noise bandwidth to a fixed value determined by the lower bound of the allowable range of carrier-to-noise power ratio, so that it is difficult to optimally track GPS signal. In order to make up for the weak points of the fixed-type narrow loop noise bandwidth method and simultaneously minimize the error of code and carrier measurements, this paper proposes a stepwise-type adaptive bandwidth algorithm for DGPS reference receivers. In this paper, it is shown that the proposed adaptive bandwidth algorithm can provide more accurate measurements than those of the fixed-type narrow loop noise bandwidth method, in view of analyzing the simulation results between two signal tracking algorithms. This paper also carries out sensitivity analysis of the proposed adaptive bandwidth algorithm due to the estimation uncertainty of carrier-to-noise power ratio. Finally the analysis results are verified by the experiment using GPS simulator.

• 한국정보통신학회논문지
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• 제9권3호
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• pp.582-586
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• 2005

본 논문은 locking 상태에 따라서 루프대역폭이 변화하는 Phase Locked Loop (PLL)의 구조를 제안하였다. 제안한 PLL은 기본적인 PLL 블록과 NOR Gate, Inverter, Capacitor, 그리고 Schmitt trigger로 이루어진 Locking Status Indicator(LSI) 블록으로 구성되었다. LSI는 Loop Fille.(LF)에 공급되는 전류와 저항 값을 locking 상태에 따라 변화시켜서 unlock이 되면 넓은 루프대역폭 가지는 PLL로, lock이 되면 좁은 루프대역폭을 가지는 PLL로 동작하도록 한다. 이러한 구조의 PLL은 짧은 locking 시간과 저 잡음의 특성을 동시에 만족시킬 수 있다. 제안된 PLL은 Hynix CMOS $0.35{\mu}m$ 공정으로 Hspice 시뮬레이션 하였으며 40us의 짧은 locking 시간과 -76.1dBc 크기의 spur를 가진다.

• IEIE Transactions on Smart Processing and Computing
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• 제4권3호
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• pp.141-144
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• 2015

A broadband radio frequency synthesizer for multi-band, multi-standard mobile DTV tuners is proposed, it's loop bandwidth can be calibrated to optimize integrated phase noise performance without the problem of phase noise peaking. For this purpose, we proposed a new third-order scalable loop filter and a scalable charge pump circuit to minimize the variation in phase margin during calibration. The prototype phase-lock loop is fabricated in 180nm complementary metal-oxide semiconductor shows that it effectively prevents phase noise peaking from growing while the loop bandwidth increases by up to three times.

• 한국통신학회논문지
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• 제28권12A호
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• pp.983-990
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• 2003

본 논문에서는 3GPP 모뎀용 비동기식 동기추적회로(noncoherent code tracking loop)를 설계하고 설계된 회로의 정상상태 지터 분산(steady-state jitter variance)과 과도응답 특성(transient response characterisitc)을 해석한다. 먼저, AWGN 환경에서의 지터 분산을 펄스성형 필터(pulse-shaping filter), 타이밍 오프셋(timing offset), 신호 대잡음비(signal-to-interference ratio), 루우프 대역폭(loop bandwidth)에 대한 일반식으로 유도하고, 과도응답 특성을 이론적으로 해석한다. 이를 바탕으로, 디지털 하드웨어 구현이 용이한 가변 대역폭 동기추적회로를 설계하며 설계된 회로와 고정 대역폭 시스템의 성능을 이론적으로 비교, 분석하고 컴퓨터 시뮬레이션을 통해 검증한다.

• International Journal of Control, Automation, and Systems
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• 제6권6호
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• pp.948-953
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• 2008

In high dynamic situations, the GPS carrier tracking loop requires a wide bandwidth to track a carrier signal because the Doppler frequency changes more rapidly with time. However, a wide bandwidth allows noises within the bandwidth of the tracking loop to pass through the loop filter. As these noises are used in the numerical controlled oscillator(NCO), the carrier tracking loop of a GPS receiver shows a degraded performance in high dynamic situations. To solve this problem, an adaptive two-stage Kalman filter, which offers the NCO a less noisy phase error, can be used. This filter is based on a carrier phase dynamic model and can adapt to an incomplete dynamic model and a quickly changed Doppler frequency. The performance of the proposed tracking loop is verified by several simulations.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.146-153
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• 2008

High speed serial link에 적합한 clock multiphase generator용 integrated phase-locked loop (PLL)을 설계하였다. 설계된 PLL은 programmable current mirror를 사용하여 동작 범위 안에서 동일한 loop bandwidth와 damping factor를 가진다. 또한 설계한 PLL 회로 netlists를 가지고 HSPICE 시뮬레이션을 통해 close-loop transfer function과 VCO의 phase noise transfer function을 구하였다. Board 위 칩의 자체 임피던스는 decoupling capacitor의 크기와 위치에 따라 계산된다. 세부적으로, close-loop transfer function에서 gain의 최대값과 VCO noise transfer function에서 gain의 최대값 사이의 주파수범위에서 decoupling capacitor의 크기와 위치에 따른 보드 위 칩의 자체 임피던스를 구하였다. 이를 바탕으로 보드에서의 decoupling capacitor의 크기와 위치가 PLL의 jitter에 어떠한 영향을 미치는지 분석하였다. 설계된 PLL은 1.8V의 동작 전압에서 400MHz에서 2GH의 wide operation range를 가지며 $0.18-{\mu}m$ EMOS공정으로 설계하였다. Reference clock은 100MHz이며 전체 PLL power consumption은 1.2GHz에서 17.28 mW이다.

• International Journal of Control, Automation, and Systems
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• 제6권4호
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• pp.596-606
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• 2008

In this paper, we present a co-design methodology of dynamic optimal network-bandwidth allocation (ONBA) and adaptive control for networked control systems (NCSs) to optimize overall control performance and reduce total network-bandwidth usage. The proposed dynamic co-design strategy integrates adaptive feedback control with real-time scheduling. As part of this co-design methodology, a "closed-loop" ONBA algorithm for NCSs with communication constraints is presented. Network-bandwidth is dynamically assigned to each control loop according to the quality of performance (QoP) information of each control loop. As another part of the co-design methodology, a network quality of service (QoS)-adaptive control design approach is also presented. The idea is based on calculating new control values with reference to the network QoS parameters such as time delays and packet losses measured online. Simulation results show that this co-design approach significantly improves overall control performance and utilizes less bandwidth compared to static strategies.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.568-576
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• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.