• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.8
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• pp.3301-3306
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• 2012

In LED chip packaging, die bonding is a very important process which fixes the LED chip on the lead frame to provide enough strength for the next process. Conventional pick-up device of the die bonder is simply operated by up and down motion of a collet and an ejector pin. However, this method may cause undesired problems such as position misalignment and/or severe die damage when the pick-up device reaches the die. In this study, to minimize the position alignment error and die damage, a die bonder is developed by adopting a new pick-up head for precise alignment and high speed feeding. To evaluate structural stability of the designed system, required finite element model of the die bonder is generated, and structural analysis is performed. Vibration analysis of the pick-up head is also performed using developed finite element model at operation frequency range. As a result of the analysis, deformation, stress, and natural frequency of the die bonder are investigated.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.6
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• pp.2624-2630
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• 2013

In LED chip packaging, die bonding is a very important process which fixes the LED chip on the lead flame to provide enough strength for the next process. During the process, inspection processes are very important to detect exact locations of dispensed epoxy dots and to determine bonding status of dies whether they are lies at exact positions with sufficient bonding strength. In this study, a useful machine vision based inspection system is proposed for the LED die bonder. In the proposed system, 2 cameras are used for epoxy dot position detection and 2 cameras are sued for die attaching status determination. New vision processing algorithm is proposed, and its efficiency is verified through required field experiments. Measured position error is less than $X:-29{\mu}m$, $Y:-32{\mu}m$ and rotation error:$3^{\circ}$ using proposed vision algorithm. It is concluded that the proposed machine vision based inspection system can be successfully implemented on the developed die bonding system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.4
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• pp.175-182
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• 2017

In light emitting diode (LED) chip packaging, wire bonding is an important process that connects the LED chip on the lead frame pad with the Au wire and enables electrical operation for the next process. The wire bonding process is divided by two types: thermo compression bonding and ultrasonic bonding. Generally, the wire bonding process consists of three steps: 1st ball bonding that bonds the shape of the ball on the LED chip electrode, looping process that hangs the wire toward another connecting part with a loop shape, and 2nd stitch bonding that forms and bonds to another electrode. This study analyzed the factors affecting the LED die bonding processes to optimize the process capability that bonds a small Zener diode chip on the PLCC (plastic-leaded chip-carrier) LED package frame, and then applied response surface analysis. The design of experiment (DOE) was established considering the five factors, three levels, and four responses by analyzing the factors. As a result, the optimal conditions that meet all the response targets can be derived.

• Journal of Applied Reliability
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• v.13 no.2
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• pp.109-116
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• 2013

The solder is any of various fusible alloys, usually tin and lead, used to join metallic parts that provide the contact between the chip package and the printed circuit board. Solder plays an important role of electrical signals to communicate between the two components. In this study, two kinds of Ag-free solder as sample is made to conduct the thermal shock test and the high humidity temperature test. Low resistance is measured to estimate crack size of solder, using daisy chain. The low speed shear test is also performed to analyze strength of solder. The appropriate degradation model is estimated using the result data. Depending on the composition of solder, lifetime estimation is conducted by adopted degradation model. The lifetime estimated two kinds of Ag-free solder is compared with expected lifetime of Sn-Ag-Cu solder. The result is that both Ag-free composition are more reliable than Sn-Ag-Cu solder.

• Journal of Welding and Joining
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• v.33 no.3
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• pp.25-31
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• 2015

Due to environmental regulations (RoHS, WEEE and ELV) of the European Union, electronics and automotive electronics have to eliminate toxic substance from electronic devices and system. Specifically, reliability issue of lead-free solder joint have an increasing demand for the car electronics caused by ELV banning. The authors prepared engine control unit and cabin electronics soldered with Sn-3.0Ag-0.5Cu (SAC305). To compare with the degradation characteristics of solder joint strength, thermal cycling test (TC), power-thermal cycling test (PTC) and series tests were conducted. Series tests were conducted for TC and PTC combined stress test using the same sample in sequence and continuously. TC test was performed at $-40{\sim}125^{\circ}C$ and soak time 10 min for 1000 cycles. PTC test was applied by pulse power and full function conditions during 100 cycles. Combined stress test was tested in accordance with automotive company standard. Solder joint degradation was observed by optical microscopy and environment scanning electron microscopy (ESEM). In addition, to compare with deterioration of bond strength of quad flat package (QFP) and chip components, we have measured lead pull and shear strength. Based on the series test results, consequently, we have validated of series test method for lifetime and reliability of Pb-free solder joint in automotive electronics.

• Korean Journal of Materials Research
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• v.12 no.9
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• pp.750-760
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• 2002

In this study, three solders, Sn-37Pb, Sn-3.5Ag, and Sn-3.8Ag-0.7Cu were screen printed on both electroless Ni/Au and OSP metal finished micro-via PCBs (Printed Circuit Boards). The interfacial reaction between PCB metal pad finish materials and solder materials, and its effects on the solder bump joint mechanical reliability were investigated. The lead free solders formed a large amount of intermetallic compounds (IMC) than Sn-37Pb on both electroless Ni/Au and OSP (Organic Solderabilty Preservatives) finished PCBs during solder reflows because of the higher Sn content and higher reflow temperature. For OSP finish, scallop-like $Cu_{6}$ /$Sn_{5}$ and planar $Cu_3$Sn intermetallic compounds (IMC) were formed, and fracture occurred 100% within the solder regardless of reflow numbers and solder materials. Bump shear strength of lead free solders showed higher value than that of Sn-37Pb solder, because lead free solders are usually harder than eutectic Sn-37Pb solder. For Ni/Au finish, polygonal shaped $Ni_3$$Sn_4$ IMC and P-rich Ni layer were formed, and a brittle fracture at the Ni-Sn IMC layer or the interface between Ni-Sn intermetallic and P-rich Ni layer was observed after several reflows. Therefore, bump shear strength values of the Ni/Au finish are relatively lower than those of OSP finish. Especially, spalled IMCs at Sn-3.5Ag interface was observed after several reflow times. And, for the Sn-3.8Ag-0.7Cu solder case, the ternary Sn-Ni-Cu IMCs were observed. As a result, it was found that OSP finished PCB was a better choice for solders on PCB in terms of flip chip mechanical reliability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.1-8
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• 2012

This paper presents a fully-integrated buck converter equipped with packaging inductors. These inductors include parasitic inductances of the bonding wires and lead frames in the package. They have significantly better Q factors than the best on-chip inductors implemented on silicon. This paper also proposes a low-swing gate driver for efficient regulation of high-frequency switching converters. The low-swing driver uses the voltage drop of a diode-connect transistor. The proposed converter is designed and fabricated using a $0.13-{\mu}m$ CMOS process. The fully-integrated buck converter achieves 68.7% and 86.6% efficiency for 3.3 V/2.0 V and 2.8 V/2.3 V conversions, respectively.

• Korean Journal of Materials Research
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• v.17 no.3
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• pp.152-159
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• 2007

When the electronics are tested with thermal shock for Pb-free solder joint reliability, there are temperature conditions with use environment but number of cycles for test don't clearly exist. To obtain the long term reliability data, electronic companies have spent the cost and times. Therefore this studies show the test method and number of thermal shock cycles for evaluating the solder joint reliability of electronic components and also research bonding strength variation with formation and growth of intermetallic compounds (IMC). SMD (surface mount device) 3216 chip resistor and 44 pin QFP (quad flat package) was utilized for experiments and each components were soldered with Sn-40Pb and Sn-3.0 Ag-0.5 Cu solder on the FR-4 PCB(printed circuit board) using by reflow soldering process. To reliability evaluation, thermal shock test was conducted between $-40^{\circ}C\;and\;+125^{\circ}C$ for 2,000 cycles, 10 minute dwell time, respectively. Also we analyzed the IMCs of solder joint using by SEM and EDX. To compare with bonding strength, resistor and QFP were tested shear strength and $45^{\circ}$ lead pull strength, respectively. From these results, optimized number of cycles was proposed with variation of bonding strength under thermal shock.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.19-27
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• 2003

Surface finishes of PCB laminates are important in the solder joint reliability of flip chip package because the types and thicknesses of intermetallic compound(IMC), and compositions and hardness of solders are affected by them. In this study, effects of surface finishes of PCB on the low cycle fatigue resistance of Sn-based lead-free solders; Sn-3.5Ag, Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag-XBi(X=2.5, 7.5) and Sn-0.7Cu were investigated for the Cu and Au/Ni surface finish treatments. Displacement controlled room temperature lap shear fatigue tests showed that fatigue resistance of Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag and Sn-0.7Cu alloys were more or less the same each other but much better than that of Bi containing alloys regardless of the surface finish layer used. In general, solder joints on the Au/Ni finish showed better fatigue resistance than those on the Cu finish. Cross-sectional fractography revealed microcracks nucleation inside of the interfacial IMC near the solder mask edge, more frequently on the Cu than the Au/Ni surface finish. Macro cracks followed the solder/IMC interface in the Bi containing alloys, while they propagated in the solder matrix in other alloys. It was ascribed to the Bi segregation at the solder/IMC interface and the solid solution hardening effect of Bi in the $\beta-Sn$ matrix.