• Title/Summary/Keyword: latch-up

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Analysis of The Dual-Emitter LIGBT with Low Forward Voltage Loss and High Lacth-up Characteristics (낮은 순방향 전압 강하와 높은 래치-업 특성을 갖는 이중-에미터 구조의 LIGBT에 관한 분석)

  • Jung, Jin-Woo;Lee, Byung-Seok;Park, San-Cho;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.15 no.2
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    • pp.164-170
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    • 2011
  • In this paper, we present a novel Lateral Insulated-Gate Bipolar Transistor(LIGBT) structure. The proposed structure has extra emitter between emitter and collector of the conventional structure. The added emitter can significantly improve latch-up current densities, forward voltage drop (Vce,sat) and turn-off characteristics. From the simulation results, the proposed LIGBT has the lower forward voltage drop(1.05V), the higher latch-up current densities($2.5{\times}10^3\;A/{\mu}m^2$), and the shorter turn-off time(7.4us) than those of the conventional LIGBT.

The novel NPLVTSCR ESD ProtectionCircuit without Latch-up Phenomenon for High-Speed I/O Interface (Latch-up을 방지한 고속 입출력 인터페이스용 새로운 구조의 NPLVTSCR ESD 보호회로)

  • Koo, Yong-Seo
    • Journal of IKEEE
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    • v.11 no.1 s.20
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    • pp.54-60
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    • 2007
  • In this study novel ESD protection device, namely, N/P-type Low Voltage Triggered SCR, has been proposed, for high speed I/O interface. Proposed device could lower high trigger voltage($\sim$20V) of conventional SCR and reduce latch-up phenomenon of protection device during the normal condition. In this Study, the proposed NPLVTSCR has been simulated using TMA MEDICI device simulator for electrical characteristic. Also the proposed device's test pattern was fabricated using 90nm TSMC's CMOS process and was measured electrical characteristic and robustness. In the result, NPLVTSCR has 3.2V $\sim$ 7.5V trigger voltage and 2.3V $\sim$ 3.2V holding voltage by changing PMOS gate length and it has about 2kV, 7.5A HBM ESD robustness(IEC61000-4-2).

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A Study on ESD Protection Circuit with Bidirectional Structure with Latch-up Immunity due to High Holding Voltage (높은 홀딩 전압으로 인한 래치업 면역을 갖는 양방향 구조의 ESD 보호회로에 관한 연구)

  • Jung, Jang-Han;Do, Kyung-Il;Jin, Seung-Hoo;Go, Kyung-Jin;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.25 no.2
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    • pp.376-380
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    • 2021
  • In this paper, we propose a novel ESD protection device with Latch-up immunity properties due to high holding voltages by improving the structure of a typical SCR. To verify the characteristics of the proposed ESD circuit, simulations were conducted using Synopsys TCAD and presented compared to existing ESD protection circuits. Furthermore, the variation of electrical properties was verified using the design variable D1. Simulation results confirm that the proposed ESD protective circuit has higher holding voltage properties and bidirectional discharge properties compared to conventional ESD protective circuits. We validate the electrical properties with post-design TLP measurements using Samsung's 0.13um BCD process. And we verify that the proposed ESD protection circuit in this paper is well suited for high voltage applications in that it has a latch-up immunity due to improved holding voltage through optimization of design variables.

A Design of High-speed Power-off Circuit and Analysis (고속 전원차단 회로 설계 제작 및 측정)

  • Jeong, Sang-Hun;Lee, Nam-Ho;Cho, Seong-Ik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.63 no.4
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    • pp.490-494
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    • 2014
  • In this paper, a design of high-speed power-off circuit and analysis. The incidence of high-dose transient radiation into the silicon-based semiconductor element induces the photocurrent due to the creation of electron-hole pairs, which causes the upset phenomenon of active elements or triggers the parasitic thyristor in the element, resulting in latch-up. High speed power-off circuit was designed to prevent burn-out of electronic device caused by Latch-up. The proposed high speed power-off circuit was configured with the darlington transistor and photocoupler so that the power was interrupted and recovered without the need for an additional circuit, in order to improve the existing problem of SCR off when using the thyristor. The discharge speed of the high speed power interruption circuit was measured to be 19 ${\mu}s$ with 10 ${\mu}F$ and 500 ${\Omega}$ load, which was 98% shorter than before (12.8 ms).

Optimal P-Well Design for ESD Protection Performance Improvement of NESCR (N-type Embedded SCR) device (NESCR 소자에서 정전기 보호 성능 향상을 위한 최적의 P-Well 구조 설계)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
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    • v.9 no.3
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    • pp.15-21
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    • 2014
  • An electrostatic discharge (ESD) protection device, so called, N-type embedded silicon controlled rectifier (NESCR), was analyzed for high voltage operating I/O applications. A conventional NESCR standard device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latch-up problem during normal operation. However, our modified NESCR_CPS_PPW device with proper junction/channel engineering such as counter pocket source (CPS) and partial P-well structure demonstrates highly latch-up immune current-voltage characteristics with high snapback holding voltage and on-resistance.

New Approach for Transient Radiation SPICE Model of CMOS Circuit

  • Jeong, Sang-Hun;Lee, Nam-Ho;Lee, Jong-Yeol;Cho, Seong-Ik
    • Journal of Electrical Engineering and Technology
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    • v.8 no.5
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    • pp.1182-1187
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    • 2013
  • Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.

Simulation-based ESD protection performance of modified DDD_NSCR device with counter pocket source structure for high voltage operating I/O application (고전압 동작용 I/O 응용을 위해 Counter Pocket Source 구조를 갖도록 변형된 DDD_NSCR 소자의 ESD 보호성능 시뮬레이션)

  • Seo, Yong-Jin;Yang, Jun-Won
    • Journal of Satellite, Information and Communications
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    • v.11 no.4
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    • pp.27-32
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    • 2016
  • A conventional double diffused drain n-type MOSFET (DDD_NMOS) device shows SCR behaviors with very low snapback holding voltage and latch-up problem during normal operation. However, a modified DDD_NMOS-based silicon controlled rectifier (DDD_NSCR_CPS) device with a counter pocket source (CPS) structure is proven to increase the snapback holding voltage and on-resistance compare to standard DDD_NSCR device, realizing an excellent electrostatic discharge protection performance and the stable latch-up immunity.

A Small Scaling Lateral Trench IGBT with Improved Electrical Characteristics for Smart Power IC (스마트 파워 IC를 위한 향상된 전기특성의 소규모 횡형 트랜치 IGBT)

  • 문승현;강이구;성만영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.267-270
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    • 2001
  • A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10$\mu\textrm{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sifted conventional LTIGBT and the conventional LTIGBT which has the width of 17$\mu\textrm{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17$\mu\textrm{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field in the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

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Electrical Characteristics of Novel LIGBT with p Channel Gate and p+ Ring at Reverse Channel Structure (p+링과 p 채널 게이트를 갖는 역채널 LIGBT의 전기적인 특성)

  • Gang, Lee-Gu;Seong, Man-Yeong
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.51 no.3
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    • pp.99-104
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    • 2002
  • lateral insulated gate bipolar transistors(LIGBTs) are extensively used in high voltage power IC application due to their low forward voltage drops. One of the main disadvantages of the LIGBT is its scow switching speed when compared to the LDMOSFET. And the LIGBT with reverse channel structure is lower current capability than the conventional LIGBT at the forward conduction mode. In this paper, the LIGBT which included p+ ring and p-channel gate is presented at the reverie channel structure. The presented LIGBT structure is proposed to suppress the latch up, efficiently and to improve the turn off time. It is shown to improve the current capability too. It is verified 2-D simulator, MEDICI. It is shown that the latch up current of new LIGBT is 10 times than that of the conventional LIGBT Additionally, it is shown that the turn off characteristics of the proposed LIGBT is i times than that of the conventional LIGBT. It is net presented the tail current of turn off characteristics at the proposed structure. And the presented LIGBT is not n+ buffer layer because it includes p channel gate and p+ ring.

Improvement of ESD (Electrostatic Discharge) Protection Performance of NEDSCR (N-Type Extended Drain Silicon Controlled Rectifier) Device using CPS (Counter Pocket Source) Ion Implantation (CPS 이온주입을 통한 NEDSCR 소자의 정전기 보호 성능 개선)

  • Yang, Jun-Won;Seo, Yong-Jin
    • Journal of Satellite, Information and Communications
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    • v.8 no.1
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    • pp.45-53
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    • 2013
  • An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latch-up problem during normal operation. However, a modified NEDSCR device with proper junction/channel engineering using counter pocket source (CPS) ion implantation demonstrates itself with both the excellent ESD protection performance and the high latch-up immunity. Since the CPS implant technique does not change avalanche breakdown voltage, this methodology does not reduce available operation voltage and is applicable regardless of the operation voltage.