• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.6
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• pp.38-48
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• 1993

A recessed n-p Juction diode with the self-aligned sturcture is proposed and fabricated by using the polysilicon as an n$^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar divice and the n$^{+}$ polysilicone mitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition. As$^{+}$ dose for the doping of the polysilicon and the annealing condition using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS and the electrical characteristics are analyzed in terms of the ideality factor of diode (n), contact resistance and reverse leakage current. In addition, n$^{+}$-p junction diodes are formed by using the amorphous silicon (of combination of amorphous and polysiliocn) instead of polysilicon and their characteristics are compared with those of the standard sample. The As$^{+}$ dose for the formation of good junction is about 1~2${\times}10^{16}cm^{2}$ at given RTA conditions (1100.deg. C, 10sec).

• Journal of the Korean Vacuum Society
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• v.14 no.1
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• pp.29-34
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• 2005

The degradation of the SiGe hetero-junction bipolar transistor(HBT) properties in SiGe BiCMOS process was investigated in this paper. The SiGe HBT prepaired by SiGe BiCMOS process, unlike the conventional one, showed the degraded DC characteristics such as the decreased Early voltage, the decreased collector-emitter breakdown voltage, and the highly increased base leakage current. Also, the cutoff frequency(f/sub T/) and the maximum oscillation frequency(f/sub max/) representing the AC characteristics are reduced to below 50%. These deteriorations are originated from the change of the locations of emitter-base and collector-base junctions, which is induced by the variation of the doping profile of boron in the SiGe base due to the high-temperature source-drain annealing. In the result, the junctions pushed out of SiGe region caused the parastic barrier formation and the current gain decrease on the SiGe HBT device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.69-75
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• 2003

Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.390-396
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• 2003

As the design rule of device continued to shrink, the contact resistance in small contact size became important. Although the conventional TiN/Ti structure as a ohmic layer has been widely used, we propose a new TiN/Co film structure. We characterized a contact resistance by using a chain pattern and a KELVIN pattern, and a leakage current determined by current-voltage measurements. Moreover, the microstructure of TiN/ Ti/ silicide/n$\^$+/ contact was investigated by a cross-sectional transmission electron microscope (TEM). The contact resistance by the Co ohmic layer showed the decrease of 26 % compared to that of a Ti ohmic layer in the chain resistance, and 50 ％ in KELYIN resistance, respectively. A Co ohmic layer shows enough ohmic behaviors comparable to the Ti ohmic layer, while higher leakage currents in wide area pattern than Ti ohmic layer. We confirmed that an uniform silicide thickness and a good interface roughness were able to be achieved in a CoSi$_2$ Process formed on a n$\^$+/ silicon junction from TEM images.

• Solar Energy
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• v.8 no.2
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• pp.12-18
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• 1988

The effect of surface recombination current density on the saturation current density in Si solar cell has been studied. Theoretical model for surface recombination current was set up from emitter transparent model of M.A. Shibib, and saturation current of Si solar cell made by ion implantation method was also measured by digital electrometer. The theoretical surface recombination current density which is the same as saturation surface recombination current density in Shibib model was $10^{-11}[A/cm^2]$ and the measured value was ranged from $8{\times}10^{-10}$ to $2{\times}10^{-9}[A/cm^2]$. Comparing with the ideal p-n junction of Shockley, transparent emitter model shows improved result by $10^2$ order of saturation current density. But there still exists $10^2$ order of difference of saturation current density between theoretical and actual values, which are assumed to be caused by 1) leakage current through solar cell edge, 2) recombination of carriers in the depletion layer, 3) the series resistance effect and 4) the tunneling of carriers between states in the band gap.

• Korean Journal of Materials Research
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• v.8 no.4
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• pp.288-292
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• 1998

The p*-n ultra shallow junction diode with Co/Ti bilayer silicide was formed by ion implantation of $BF_{2}$ energy : 30KeV, dose : $5\times10^{15}cm^{-2}$] onto the n-well Si(100) region and RTA-silicidation of the evaporated Co($120\AA$)/Ti($40\AA$) double layer. The fabricated diode exhibited ideality factor of 1.06, specific contact resistance of $1.2\times10^{-6}\Omega\cdot\textrm{cm}^2$ and leakage current of $8.6\muA/\textrm{cm}^2$(-3V) under the reverse bias of 3V. The sheet resistance of silicided emitter region, the boron concentration at silicide/Si interface and the junction depth including silicide layer of ($500\AA$ were about $8\Omega\Box$, $6\times10^{19}cm^{-3}$, and $0.14\mu{m}$, respectively. In the fabrication of diode, the application of Co/Ti bilayer silicide brought improvement of ideality factor on the current-voltage characteristics as well as reduction of emitter sheet resistance and specific contact resistance, while it led to a little increase of leakage current.

• Journal of the Semiconductor & Display Technology
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• v.6 no.3
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• pp.47-53
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• 2007

Ultra thin Si p-n junctions shallower than $300{\AA}$ were fabricated and biased to the avalanche regime. The ultra thin junctions were fabricated to be parallel to the surface and exposed to the surface without $SiO_2$ layer. Those junctions emitted white light and electrons when junctions were biased in the avalanche breakdown regime. Therefore, we could observe the avalanche breakdown region visually. We could also observe the influence of electric field to the current flow visually by observing the white light which correspond to the avalanche breakdown region. Arrayed diodes emit light and electrons uniformly at the diode area. But, the reverse leakage current were larger than those of ordinary diodes, and the breakdown voltage were less than 10V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.495-502
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• 2014

Fast recovery diodes (FRDs) were developed using the $p^{{+}{+}}/n^-/n^{{+}{+}}$ epitaxial layers grown by low temperature epitaxy technology. We investigated the effect of electrostatic discharge (ESD) stresses on their electrical and switching properties using current-voltage (I-V) and reverse recovery time analyses. The FRDs presented a high breakdown voltage, >450 V, and a low reverse leakage current, < $10^{-9}$ A. From the temperature dependence of thermal activation energy, the reverse leakage current was dominated by thermal generation-recombination and diffusion, respectively, at low and high temperature regions. By virtue of the abrupt junction and the Pt drive-in for the controlling of carrier lifetime, the soft reverse recovery behavior could be obtained along with a well-controlled reverse recovery time of 21.12 ns. The FRDs exhibited excellent ESD robustness with negligible degradations in the I-V and the reverse recovery characteristics up to ${\pm}5.5$ kV of HBM and ${\pm}3.5$ kV of IEC61000-4-2 shocks. Likewise, transmission line pulse (TLP) analysis reveals that the FRDs can handle the maximum peak pulse current, $I_{pp,max}$, up to 30 A in the forward mode and down to - 24 A in the reverse mode. The robust ESD property can improve the long term reliability of various power applications such as automobile and switching mode power supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.367-370
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• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1281-1286
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• 2006

We have used the silicon-carbide(4H-SiC) instead of conventional silicon materials to develope of the planar junction barrier schottky rectifier for ultra high breakdown voltage(1,200 V grade). The substrate size is 2 inch wafer, Its concentration is $3*10^{18}/cm^{3}$ of $n^{+}-$type, thickness of epitaxial layer $12{\mu}m$ conentration is $5*10^{15}cm^{-3}$ of n-type. The fabticated devices are junction barrier schottky rectifier, The guard ring for improvement of breakdown voltage is designed by the box-like impurity of boron, the width and space of guard ring was designed by variation. The contact metals to rectify were used by the $Ni(3,000\:{\AA})/Au(2,000\:{\AA})$. As a results, the on-state voltage is 1.26 V, on-state resistance is $45m{\Omega}/cm^{3}$, maximum value of improved reverse breakdown voltage is 1180V, reverse leakage current density is $2.26*10^{-5}A/CM^{3}$. We had improved the measureme nt results of the electrical parameters.