• Title/Summary/Keyword: interconnect testing

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New IEEE 1149.1 Boundary Scan Architecture for Multi-drop Multi-board System (멀티 드롭 멀티 보드 시스템을 위한 새로운 IEEE 1149.1 경계 주사 구조)

  • Bae, Sang-Min;Song, Dong-Sup;Kang, Sung-Ho;Park, Young-Ho
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.49 no.11
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    • pp.637-642
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    • 2000
  • IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

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A New Test Algorithm for Effective Interconnect Testing Among SoC IPs (SoC IP 간의 효과적인 연결 테스트를 위한 알고리듬 개발)

  • 김용준;강성호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.1
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    • pp.61-71
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    • 2003
  • Interconnect test for highly integrated environments like SoC, becomes more important as the complexity of a circuit increases. This importance is from two facts, test time and complete diagnosis. Since the interconnect test between IPs is based on the scan technology such as IEEE1149.1 and IEEE P1500, it takes long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue because a defect on interconnects are shown as a defect on a chip. But generally, interconnect test algorithms that need the short test time can not do complete diagnosis and algorithms that perform complete diagnosis need long test time. A new interconnect test algorithm is developed. The new algorithm can provide a complete diagnosis for all faults with shorter test length compared to the previous algorithms.

Efficient Interconnect Test Patterns and BIST Implementation for Crosstalk and Static Faults (Crosstalk과 정적 고장을 고려한 효과적인 연결선 테스트 알고리즘 및 BIST 구현)

  • Min Pyoungwo;Yi Hyunbean;Song Jaehoon;Park Sungju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.7 s.337
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    • pp.37-44
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    • 2005
  • This paper presents effective test patterns and their BIST implementations for SoC and Board interconnects. Initially '6n'algorithm, where 'n' is the total number of interconnect nets, is introduced to completely detect and diagnose both static and crosstalk faults. Then, more economic 4n+1 algorithm is described to perfectly capture the crosstalk faults for the interconnect nets separated within a certain distance. It will be shown that both algorithms can be easily implemented as interconnect BIST hardwares with small area penalty than conventional LFSR.

Wrapper Cell Design for Redundancy TSV Interconnect Test (Redundancy TSV 연결 테스트를 위한 래퍼셀 설계)

  • Kim, Hwa-Young;Oh, Jung-Sub;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.8
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    • pp.18-24
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    • 2011
  • A new problem happens with the evolution of TSV based 3D IC design. The bonding process takes place which follows with the testing of design for proper connectivity in the absence of TSV redundancy. In order to achieve good yield, the design should be tested with redundancy TSV. This paper presents a wrapper cell design for redundancy TSV interconnect test. The design for test technique, in terms of hardware and software perspectives is described. The wrapper cell with hardware design can use original test patterns. However, software design has less area overhead.

On-line Bus Monitoring of a System Using Bondary-Scan (경계스캔 구조를 사용한 시스템의 온라인 버스 모니터링)

  • Song, Dong-Sup;Bae, Sang-Min;Kang, Sung-Ho;Park, Young-Ho
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.49 no.12
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    • pp.675-682
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    • 2000
  • When a system is composed of multi-boards, an efficient bus arbitration method for the data transfer bus must be provided for guaranteeing proper operations. In this paper, a new test methodology is developed which is used for testing on-line bus arbitration. In the new test methodology, events that are occurred during bus arbitration are defined, and expected signals during fault-free bus arbitration are compared with the signals captured during on-line bus arbitration using boundary-scan cells. For this, a new test architecture is proposed which is efficient for the maintenance and the repair of multi-board systems. In addition, the new methodology can be used with off-line interconnect test using boundary-scan.

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CSP + HDI : MCM!

  • Bauer, Charles-E.
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2000.04a
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    • pp.35-40
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    • 2000
  • MCM technology languished troughout most of the 1990's due to high costs resulting from low yields and issues with known god die. During the last five years of the decade new developments in chip scale packages and high density, build up multi-layer printed wiring boards created new opportunities to design and produce ultra miniaturized modules using conventional surface mount manufacturing capabilities. Focus on the miniaturization of substrate based packages such as ball grid arrays (BGAs) resulted in chip scale packages (CSPs) offering many of the benefits of flip chip along with the handling, testing, manufacturing and reliability capabilities of packaged deviced. New developments in the PWB industry sought to reduce the size, weight, thickness and cost of high density interconnect (HDI) substrates. Shrinking geometries of vias and new constructions significantly increased the interconnect density available for MCM-L applications. This paper describes the most promising CSP and HDI technologies for portable products, high performance computing and dense multi-chip modules.

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A Clustered Reconfigurable Interconnection Network BIST Based on Signal Probabilities of Deterministic Test Sets (결정론적 테스트 세트의 신호확률에 기반을 둔 clustered reconfigurable interconnection network 내장된 자체 테스트 기법)

  • Song Dong-Sup;Kang Sungho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.12
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    • pp.79-90
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    • 2005
  • In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST to improve the embedding probabilities of random-pattern-resistant-patterns. The proposed method uses a scan-cell reordering technique based on the signal probabilities of given test cubes and specific hardware blocks that increases the embedding probabilities of care bit clustered scan chain test cubes. We have developed a simulated annealing based algorithm that maximizes the embedding probabilities of scan chain test cubes to reorder scan cells, and an iterative algorithm for synthesizing the CRIN hardware. Experimental results demonstrate that the proposed CRIN BIST technique achieves complete fault coverage with lower storage requirement and shorter testing time in comparison with the conventional methods.

Exploiting an On/off-Chip Bus Bridge for an Efficiently Testable SoC (효율적인 SoC 테스트를 위한 온/오프-칩 버스 브리지 활용기술에 대한 연구)

  • Song, Jae-Hoon;Han, Ju-Hee;Kim, Byeong-Jin;Jeong, Hye-Ran;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.105-116
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    • 2008
  • Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, we propose an efficient test access mechanism that exploits an on/off-chip bus bridge for the Advanced High-performance Bus (AHB) and Peripheral Component Interconnect (PCI) bus. The test application time is considerably reduced by providing dedicated test stimuli input paths and response output paths, and by excluding the bus direction tumaround delays. Experimental results show that area overhead and testing times are considerably reduced in both functional and structural test modes. The proposed technique can be a lied to the other types of on/off-chip bus bridges.

Improving Parallel Testing Efficiency of Memory Chips using NOC Interconnect (NOC 인터커넥트를 활용한 메모리 반도체 병렬 테스트 효율성 개선)

  • Hong, Chaneui;Ahn, Jin-Ho
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.68 no.2
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    • pp.364-369
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    • 2019
  • Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed as test interface architecture between DUTs and ATE. Because NOC can be extended freely, there is no limit on the number of DUTs tested at the same time. Thus, more memory can be tested with the same bandwidth of ATE. Furthermore, the proposed NOC-based parallel test method can increase the efficiency of channel usage by packet type data transmission.

Development of Simple Reconfigurable Access Mechanism for SoC Testing (재구성 가능한 시스템 칩 테스트 제어기술의 개발)

  • 김태식;민병우;박성주
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.8
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    • pp.9-16
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    • 2004
  • For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.