Browse > Article

Efficient Interconnect Test Patterns and BIST Implementation for Crosstalk and Static Faults  

Min Pyoungwo (Department of Computer Science ' Engineering, Hanyang University)
Yi Hyunbean (Department of Computer Science ' Engineering, Hanyang University)
Song Jaehoon (Department of Computer Science ' Engineering, Hanyang University)
Park Sungju (Department of Electronical Engineering Computer Science, Hanyang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.7, 2005 , pp. 37-44 More about this Journal
Abstract
This paper presents effective test patterns and their BIST implementations for SoC and Board interconnects. Initially '6n'algorithm, where 'n' is the total number of interconnect nets, is introduced to completely detect and diagnose both static and crosstalk faults. Then, more economic 4n+1 algorithm is described to perfectly capture the crosstalk faults for the interconnect nets separated within a certain distance. It will be shown that both algorithms can be easily implemented as interconnect BIST hardwares with small area penalty than conventional LFSR.
Keywords
interconnect testing; crosstalk faults; test pattern generator; BIST; SoC; static faults;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Yongjoon Kim; Hyun-don Kim; Sungho Kang, 'A new maximal diagnosis algorithm for interconnect', Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Volume 12, Issue 5, pp. 532 - 537, May 2004   DOI   ScienceOn
2 A. Hassan and J. Rajski and V.K. Agrawal, 'Testing and Diagnosis of Interconnects using Boundary Scan Architecture' Proceedings International Test Conference, pp.126-137. 1988   DOI
3 Sirisaengtaksin and Sandeep K. Gupta 'Enhanced crosstalk fault model and methodology to generate tests for arbitrary inter-core interconnect topology' Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian, 18-20 pp. 163 - 169, Nov. 2002
4 N. Jarwala and C.W. Yau, 'A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects' Test Conference, Proceedings, International, pp. 63-70, Aug. 1989   DOI
5 K. Sekar and S. Dey, 'LI-BIST: a low-cost self-test scheme for SoC logic cores and interconnects,' VLSI Test Symposium, (VTS 2002). Proceedings 20th IEEE, pp. 417 - 422, 28 April- 2 May 2002   DOI
6 R. Pendurkar and A. Chatterjee and Y. Zorian, 'Switching activity generation with automated BIST synthesis for performance testing of interconnects,' Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume 20, pp. 1143 - 1158, Sept. 2001   DOI   ScienceOn
7 Yi Zhao; Dey, S., 'Fault-coverage analysis techniques of interconnects crosstalk in chip', Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 22, pp. 770 - 782, June, 2003   DOI   ScienceOn
8 M. Cuviello, S.Dey, X.Bai, and Y.Zhao, 'Fault modeling and simulation for crosstalk in system-on-chip interconnects', In Proc. Int. Conf. Computer-Aided Design, pages 297-303, Nov. 1999   DOI
9 Xiaoliang Bai and S. Dey and J. Rajski, 'Self-test methodology for at-speed test of crosstalk in chip interconnects,' Design Automation Conference, Proceedings 2000. 37th, pp. 619 - 624, June 5-9, 2000
10 W. T. Cheng, J. L. Lewandowski and E. Wu, 'Optimal Diagnostic Methods for Wiring Interconnects' IEEE Transactions on Computer-Aided Design, Vol 11, No.9, pp. 1161-1166, Sept. 1992   DOI   ScienceOn