• 한국정보과학회논문지:정보통신
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• 제35권6호
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• pp.549-556
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• 2008

멀티미디어 통신에서 융통성 있는 비주얼 콘텐츠를 제공하기 위해 ISO/IEC MPEG & ITU-T VCEG의 JVT는 H.264/AVC 표준에 기반을 둔 확장 형식으로 SVC를 표준화하였다. JVT는 H.264/AVC SVC의 압축 효율을 높이기 위해 기존 H.264/AVC에서 제공하는 인터 예측(inter prediction) 과 인트라 예측(intra prediction) 뿐만 아니라 계층 간의 중복요소을 제거하는 계층 간 예측을 추가로 수행한다. 계층 간 예측 방법은 기본계층에서 코딩된 데이타를 재사용하여 향상계층의 비트율-왜곡(rate-distortion) 효율을 향상시킨다. 그러나 계층 간 예측을 추가로 수행함으로써 계산 복잡도가 높아지는 문제점이 있다. 본 논문에서는 이러한 계산 복잡도를 감소시키기 위해 계층 간 예측 중 기본계층의 잔여 신호값을 이용하는 예측 과정에서 효율적인 잔여신호 업 샘플링의 기법을 제안한다. 실험 결과 코딩 효율을 유지하면서 예측과정의 계산복잡도를 약 30% 줄일 수 있었다.

• 전자공학회논문지D
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• 제36D권10호
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• pp.9-16
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• 1999

Flash EEPROM 셀에서 기존의 ONO 구조의 IPD를 사용하면 peripheral MOSFET의 게이트 산화막을 성장할 때에 사용되는 세정 공정을 인하여 ONO 막의 상층 산화막이 식각되어 전하 보존 특성이 크게 열화되었으나 IPD 공정에 ONON 막을 사용하면 그 세정 공정시에 상층 질화막이 상층 산호막이 식각되는 것을 방지시켜 줌으로 전하보존 특성이 크게 개선되었다. ONON IPD 막을 갖고 있는 Flash EEPROM 셀의 전화 보존 특성의 모델링을 위하여 여기서는 굽는(bake) 동안의 전하 손실로 인한 문턱전압 감소의 실험식으로 ${\Delta}V_t\; = \;{\beta}t^me^{-ea/kT}$을 사용하였으며, 측정 결과 ${\beta}$=184.7, m=0.224, Ea=0.31 eV의 값을 얻었다. 이러한 0.31 eV의 활성화 에너지 값은 굽기로 인한 문턱전압의 감소가 층간 질화막 내에서의 트립된 전자들의 이동에 의한 것임을 암시하고 있다. 한편, 그 모델을 사용한 전사 모사의 결과는 굽기의 thermal budget이 낮은 경우에 실험치와 잘 일치하였으나, 반면에 높은 경우에는 측정치가 전사 모사의 결과보다 훨씬 더 크게 나타났다. 이는 thermal budge가 높은 경우에는 프로그램시에 층간 질화막 내에 트립되어 누설전류의 흐름을 차단해 주었던 전자들이 빠져나감으로 인하여 터널링에 의한 누설전류가 발생하였기 때문으로 보여졌다. 이러한 누설전류의 발생을 차단하기 위해서는 ONON 막 중에서 층간 질화막의 두께는 가능한 얇게 하고 상층 산화막의 두께는 가능한 두껍게 하는 것이 요구된다.

• 센서학회지
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• 제29권1호
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• pp.14-18
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• 2020

This study investigates the nitrogen dioxide (NO₂) sensing characteristics of an Si MOSFET gas sensor with a tungsten trioxide (WO₃) sensing layer deposited using the sputtering method. The Si MOSFET gas sensor consists of a horizontal floating gate (FG) interdigitated with a control gate (CG). The WO₃ sensing layer is deposited on the interdigitated CG-FG of a field effect transistor(FET)-type gas sensor platform. The sensing layer is deposited with different thicknesses of the film ranging from 100 nm to 1 ㎛ by changing the deposition times during the sputtering process. The sensing characteristics of the fabricated gas sensor are measured at different NO₂ concentrations and operating temperatures. The response of the gas sensor increases as the NO₂ concentration and operating temperature increase. However, the gas sensor has an optimal performance at 180℃ considering both response and recovery speed. The response of the gas sensor increases significantly from 24% to 138% as the thickness of the sensing layer increases from 100 nm to 1 ㎛. The sputtered WO₃ film consists of a dense part and a porous part. As reported in previous work, the area of the porous part of the film increases as the thickness of the film increases. This increased porous part promotes the reaction of the sensing layer with the NO₂ gas. Consequently, the response of the gas sensor increases as the thickness of the sputtered WO₃ film increases.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.445-448
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• 2006

Bias stress effect in pentacene organic thin-flim transistors with cross-linked PVA gate dielectric is analyzed. For negative gate bias stress, positive threshold voltage shift is observed. The injected charges from the gate electrode to the defect states of gate dielectric are regarded as the main origin of $V_T$ shift. The reduced bias stress effect using $SiO_2$ blocking layer confirms the assumed mechanism. It is also demonstrated that the inverter with $SiO_2$ blocking layer shows the negligible hysteresis owing to the reduced bias stress effect.

• Progress in Superconductivity
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• 제5권2호
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• pp.144-148
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• 2004

Uniform current distribution among conductor layers in HTS cables using IPTs (inter-phase transformers) was investigated. Conventional methods for current distribution, in which resistors are inserted to conductor layers, causes additional loss. In contrast, IPTs, which use magnetic coupling, make it possible that the current in parallel circuits is distributed uniformly with any load, and minimize the loss. In this study, IPTs were designed and fabricated for examination of uniform current distribution in the conductor layers of HTS cables. The ITP was designed through calculation of its impedance that can cancel the inductance of the conduction layers. The experimental setup consisted of four IPTs and four inductors that simulate the conductor layer inductance. Each layer was designed to feed 10 A. We examined the behavior of current distribution with IPTs for various layer inductances.

• Journal of the Optical Society of Korea
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• 제16권2호
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• pp.181-184
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• 2012

We report, for the first time, operation frequency dependence of current density-voltage ($J_{OLED}-V_{OLED}$) shift for multi-layer organic light-emitting diodes (OLEDs). When the OLEDs were electrically stressed for 21 hours with 50% duty voltage pulses at 60, 120, 240, and 360 Hz, the JOLED-VOLED shifts were suppressed by half for 360 Hz operation compared with 60 Hz operation, but with little change in emission efficiencies. This frequency dependent $J_{OLED}-V_{OLED}$ shift is believed to be commonly observed for typical multi-layer OLEDs and can be used to further improve lifetime of digitally-driven active-matrix OLED displays.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권1호
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• pp.15-22
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• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

• 마이크로전자및패키징학회지
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• 제8권2호
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• pp.19-24
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• 2001

EUV 노광공정의 반사형 노광계 및 마스크에 사용되는 Mo/Si 다층박막 착탁 시 발생하는 각 층의 두께 변화와 상호확산 층 (inter-diffusion layer)이 생성될 경우에 대하여 이들이 다층박막 반사도에 미치는 영향을 전산모사를 통하여 알아보았다. 본 연구그룹에서 개발한 다층박막 반사 시뮬레이션 프로그램을 사용하여 Mo/Si 40-period박막의 반사토플 계산한 결과, 각각의 period가 두께의 편챠(28%)를 갖는 경우, 모든 period가 같은 두께를 갖는 다층박막에 비해 최대반사도가 10.8% 감소가 되었으며 두 층간 물질 사이의 상호확산(interdiffustion) 층을 가정하였을 경우, 다층박막의 경우 그렇지 않은 경우에 비해 4.7%의 최대반사도가 감소가 예상되었다. 그리고 각 층의 적층에 따른 반사도의 변화를 시뮬레이션 프로그램을 통해 계산한 결과 반사도는 25층까지 계속 증가하며 26층부터 불규칙한 경향성을 가지며 증가와 감소를 반복함을 알 수 있었다.

• 한국실내디자인학회:학술대회논문집
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• 한국실내디자인학회 2006년도 추계학술발표대회 논문집
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• pp.125-128
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• 2006

In the history of space design, the concept and application of Multi-Layer can be easily found in various projects. As life styles in the contemporary cities are becoming more and more complex and inter-related to each other, the concept of multi-layer is re-considered In terms of constructing differentiated life patterns as well as multi programs within certain physical buildings or designs. This study aims to analyze the brief history of multi-layer in space design and the contemporary applications in recent architectural as well as interior design projects. It is concluded that the concept of multi layer is not only useful for constructing an interesting spatial organizations, but can also be a vital tool for re-organizing the contemporary urban programs that cannot be considered with the preconceived existing terms.

• 대한전자공학회논문지
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• 제24권6호
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• pp.1068-1073
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• 1987

Traditional circuit partitioning algorithm using the cluster development method, which is suitable for such applications as single chip floor planning or multiple layer PCB system placement, where the clusters are formed so that inter-cluster nets are localized within the I/O connector pins, may not be appropriate for the functiona block placement in truly 3-D electronic modules. 3-D hybrid IC is one such example where the inter-layer routing as well as the intra-layer routing can be maximally incorporated to reduce the overall circuit size, cooling requirements and to improve the speed performance. In this paper, we propose a new algorithm called MBE(Minimum Box Embedding) for the layer assignment of each functional block in 3-D hybrid IC design. The sequence of MBE is as follows` i) force-directed relaxation in 3-D space, ii) exhaustive search for the optimal orientation of the slicing plane and iii) layer assignment. The algorithm is first explaines for a 2-D reduced problem, and then extended for 3-D applications. An example result for a circuit consisting of 80 blocks has been shown.