• Journal of KIISE:Information Networking
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• v.35 no.6
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• pp.549-556
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• 2008

To achieve flexible visual content adaption for multimedia communications, the ISO/IEC MPEG & ITU-T VCEG form the JVT to develop SVC amendment for the H.264/AVC standard. JVT uses inter-layer prediction as well as inter prediction and intra prediction that are provided in H.264/AVC to remove the redundancy among layers. The main goal consists of designing inter-layer prediction tools that enable the usage of as much as possible base layer information to improve the rate-distortion efficiency of the enhancement layer. But inter layer prediction causes the computational complexity to be increased. In this paper, we proposed an efficient residual prediction. In order to reduce the computational complexity while maintaining the high coding efficiency. The proposed residual prediction uses modified interpolation that is defined in H.264/AVC SVC.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.9-16
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• 1999

When the conventional IPD (inter-poly-dielctrics) layer with ONO(oxide-nitride-oxide) structure was used in the Flash EEPROM cell, its data retention characteristics were significanfly degraded because the top oxide of the ONO layer was etched off due to the cleaning process used in the gate oxidation process for the peripheral MOSFETs. When the IPD layer with the ONON(oxide-nitride-oxide-nitride) was used there, however, its data retention characteristics were much improved because the top nitride of the ONON layer protected the top oxide from being etched in the cleaning process. For the modelling of the data retention characteristics of the Flash EEPROM cell with the ONON IPD layer, the decrease of the threshold voltage cue to the charge loss during the bake was here given by the empirical relation ${\Delta}V_t\; = \;{\beta}t^me^{-ea/kT}$ and the values of the ${\beta}$=184.7, m=0.224, Ea=0.31 eV were obtained with the experimental measurements. The activation energy of 0.31eV implies that the decrease of the threshold voltage by the back was dur to the movement of the trapped electrons inside the inter-oxide nitride layer. On the other hand, the results of the computer simulation using the model were found to be well consistent with the results of the electrical measurements when the thermal budget of the bake was not high. However, the latter was larger then the former in the case of the high thermal budger, This seems to be due to the leakage current generated by the extraction of the electrons with the bake which were injected into the inter-oxide niride later and were trapped there during the programming, and played the role to prevent the leakage current. To prevent the generation of the leakage current, it is required that the inter-oxide nitride layer and the top oxide layer be made as thin and as thick as possible, respectively.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.14-18
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• 2020

This study investigates the nitrogen dioxide (NO₂) sensing characteristics of an Si MOSFET gas sensor with a tungsten trioxide (WO₃) sensing layer deposited using the sputtering method. The Si MOSFET gas sensor consists of a horizontal floating gate (FG) interdigitated with a control gate (CG). The WO₃ sensing layer is deposited on the interdigitated CG-FG of a field effect transistor(FET)-type gas sensor platform. The sensing layer is deposited with different thicknesses of the film ranging from 100 nm to 1 ㎛ by changing the deposition times during the sputtering process. The sensing characteristics of the fabricated gas sensor are measured at different NO₂ concentrations and operating temperatures. The response of the gas sensor increases as the NO₂ concentration and operating temperature increase. However, the gas sensor has an optimal performance at 180℃ considering both response and recovery speed. The response of the gas sensor increases significantly from 24% to 138% as the thickness of the sensing layer increases from 100 nm to 1 ㎛. The sputtered WO₃ film consists of a dense part and a porous part. As reported in previous work, the area of the porous part of the film increases as the thickness of the film increases. This increased porous part promotes the reaction of the sensing layer with the NO₂ gas. Consequently, the response of the gas sensor increases as the thickness of the sputtered WO₃ film increases.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.445-448
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• 2006

Bias stress effect in pentacene organic thin-flim transistors with cross-linked PVA gate dielectric is analyzed. For negative gate bias stress, positive threshold voltage shift is observed. The injected charges from the gate electrode to the defect states of gate dielectric are regarded as the main origin of $V_T$ shift. The reduced bias stress effect using $SiO_2$ blocking layer confirms the assumed mechanism. It is also demonstrated that the inverter with $SiO_2$ blocking layer shows the negligible hysteresis owing to the reduced bias stress effect.

• Progress in Superconductivity
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• v.5 no.2
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• pp.144-148
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• 2004

Uniform current distribution among conductor layers in HTS cables using IPTs (inter-phase transformers) was investigated. Conventional methods for current distribution, in which resistors are inserted to conductor layers, causes additional loss. In contrast, IPTs, which use magnetic coupling, make it possible that the current in parallel circuits is distributed uniformly with any load, and minimize the loss. In this study, IPTs were designed and fabricated for examination of uniform current distribution in the conductor layers of HTS cables. The ITP was designed through calculation of its impedance that can cancel the inductance of the conduction layers. The experimental setup consisted of four IPTs and four inductors that simulate the conductor layer inductance. Each layer was designed to feed 10 A. We examined the behavior of current distribution with IPTs for various layer inductances.

• Journal of the Optical Society of Korea
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• v.16 no.2
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• pp.181-184
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• 2012

We report, for the first time, operation frequency dependence of current density-voltage ($J_{OLED}-V_{OLED}$) shift for multi-layer organic light-emitting diodes (OLEDs). When the OLEDs were electrically stressed for 21 hours with 50% duty voltage pulses at 60, 120, 240, and 360 Hz, the JOLED-VOLED shifts were suppressed by half for 360 Hz operation compared with 60 Hz operation, but with little change in emission efficiencies. This frequency dependent $J_{OLED}-V_{OLED}$ shift is believed to be commonly observed for typical multi-layer OLEDs and can be used to further improve lifetime of digitally-driven active-matrix OLED displays.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.15-22
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• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.19-24
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• 2001

The effect of thickness variation and inter-diffusion layer on the reflectivity of Mo/Si multilayer has been investigated. The reflectivity of the imperfect Mo/Si multilayer with thickness variation of 28% was found to be lowered by 10.8% compared to that of ideal Mo/Si multilayers with 40-periods. When the inter-diffusion layer is taken into account, the reflectivity is decreased by 4.7% additionally. We also fecund that the reflectivity continued to increase until the 25th-layer but it showed irregular tendencies about increment and decrement from the 26th-layer of Mo/Si multilayer structures.

• Proceedings of the Korean Institute of Interior Design Conference
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• 2006.11a
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• pp.125-128
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• 2006

In the history of space design, the concept and application of Multi-Layer can be easily found in various projects. As life styles in the contemporary cities are becoming more and more complex and inter-related to each other, the concept of multi-layer is re-considered In terms of constructing differentiated life patterns as well as multi programs within certain physical buildings or designs. This study aims to analyze the brief history of multi-layer in space design and the contemporary applications in recent architectural as well as interior design projects. It is concluded that the concept of multi layer is not only useful for constructing an interesting spatial organizations, but can also be a vital tool for re-organizing the contemporary urban programs that cannot be considered with the preconceived existing terms.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1068-1073
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• 1987

Traditional circuit partitioning algorithm using the cluster development method, which is suitable for such applications as single chip floor planning or multiple layer PCB system placement, where the clusters are formed so that inter-cluster nets are localized within the I/O connector pins, may not be appropriate for the functiona block placement in truly 3-D electronic modules. 3-D hybrid IC is one such example where the inter-layer routing as well as the intra-layer routing can be maximally incorporated to reduce the overall circuit size, cooling requirements and to improve the speed performance. In this paper, we propose a new algorithm called MBE(Minimum Box Embedding) for the layer assignment of each functional block in 3-D hybrid IC design. The sequence of MBE is as follows` i) force-directed relaxation in 3-D space, ii) exhaustive search for the optimal orientation of the slicing plane and iii) layer assignment. The algorithm is first explaines for a 2-D reduced problem, and then extended for 3-D applications. An example result for a circuit consisting of 80 blocks has been shown.