• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.12 no.1
• /
• pp.65-70
• /
• 2001

This paper presents a Receiver MMIC for the CDMA terminal. The complete circuit is composed of Low Noise Amplifier, Down Conversion Mixer, Intermediate Frequency Amplifier and Bias circuit. The Bias circuit implementation, which allows for compensation for threshold voltage and power supply voltage variation are provided. The proposed topology has high linearity and low noise characteristics. Results of the designed circuit are as follows: Overall conversion gain is 28.5 dB, input IP3 of LNA is 8 dBm, input IP3 of down conversion mixer is 0 dBm and total DC current consumption is 22.1 mA.

• Proceedings of the KIEE Conference
• /
• 2002.11c
• /
• pp.517-520
• /
• 2002

This paper has been studied Operational Amplification Circuit that has high power specification of 90 W is designed. In the input differential amplifier stage, the current source for circuit bias is designed to protect device from high voltage source. the criving state has the voltage gain more than input differential stage. With temperature compensation design, output stage works stable in different to temperature.

• The Journal of the Korea Contents Association
• /
• v.6 no.3
• /
• pp.38-45
• /
• 2006

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for a LCD driver IC. We apply two data to the proposed DLVDS circuit as inputs. Then, the transmitter converts two inputs to two kinds of fully differential signals. In this circuit, two transmission lines are sufficient to transfer two inputs while keeping the LVDS feature. However, the circuit has a common mode bias fluctuation due to difference of the input bias and the reference bias. We compensate the common mode bias fluctuation using a feedback circuit of the current source bias. The receiver recovers the original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25{\mu}m$ CMOS technology. The simulation results of proposed circuit shows 1-Gbps/2-line data rate and 35mW power consumption at 2.5V supply voltage, respectively.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
• /
• 2003.10a
• /
• pp.123-126
• /
• 2003

RSFQ (Rapid Single Flux Quantum) circuits are used in many practical applications. RSFQ DFFC (Delay Flip-Flop with complementary outputs) circuits can be used in a RAM, an ALU (Arithmetic Logic Unit), a microprocessor, and many communication devices. A DFFC circuit has one input, one switch input, and two outputs (output l and output 2). DFFC circuit functions in such way that output 1 follows the input and output 2 is the complement of the input when the switch input is "0." However, when there is a switch input "1."the opposite output signals are generated. In this work, we have designed an RSFQ DFFC circuit based on 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology. As circuit design tools, we used Xic, WRspice, and Lmeter After circuit optimization, we could obtain the bias current margins of the DFFC circuit to be above 32％.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.27 no.7
• /
• pp.620-624
• /
• 2016

In this paper we designed a current mode logic frequency divider to transmit a baseband amplitude modulated signal. From simulation result, we studied input and output waveforms according to the variation of input bias voltage. For the purpose of the verification of the study, we designed a current mode logic frequency divider at 1,400 MHz. The designed frequency divider operates between 100 MHz and 3,000 MHz, for -33 dBm input power. The circuit draws $I_{total}=30mA$ from $V_{DD}=3V$ supply, and the simulation result shows that an amplitude modulated signal at 1,400 MHz with the modulation index of 0.5 was successfully downconverted to 700 MHz.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.8
• /
• pp.1580-1584
• /
• 2009

We have theoretically analyzed the monolithic integration of vertical cavity lasers with depleted optical thyristor (VCL-DOT) structure and experimentally demonstrated optical logic gates such as AND-gate, OR-gate, and INVERTER implemented by VCL-DOT for an optical programmable gate array. The optical AND and OR gates have been realized by changing a input bias of the single VCL-DOTs and all kinds of optical logic functions are also implemented by adjusting an intensity of the reference input beams into the differential VCL-DOTs. To achieve the high sensitivity, high slope efficiency and low threshold current, a small active region of lasing part and a wide detecting area are simultaneously designed by using a selective oxidation process. The fabricated devices clearly show nonlinear s-shaped current-voltage characteristics and lasing characteristics of a low threshold current with 0.65 mA and output spectrum at 854 nm.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.11
• /
• pp.36-43
• /
• 2015

A pixel-level readout circuit is studied for 2-dimensional microbolometer focal plane arrays (FPAs). A current mirroring injection (CMI) input circuit with 2-step current-mode bias suppression is proposed for a pixel-level architecture with high responsivity and long integration time. The proposed circuit has been designed using a $0.35-{\mu}m$ 2-poly 4-metal CMOS process for a $320{\times}240$ microbolometer array with a pixel size of $50{\mu}m{\times}50{\mu}m$. The proposed 2-step bias-current suppression has sufficiently low calibration error with wide calibration range, and the calibration range and error can be easily optimized by controlling some design parameters. Due to high responsivity and a long integration time of more than 1 ms, the noise equivalent temperature difference (NETD) of the proposed circuit can be improved to 26 mK, which is much better than that of the conventional circuits, 67 mK.

• Proceedings of the KIEE Conference
• /
• 1999.07d
• /
• pp.1931-1933
• /
• 1999

In this paper, the current and voltage properties on the gate oxide film due to the variation of thickness are studied. The specimen is used for n-ch power MOSFET. It is shows the leakage current and current density characteristics due to the applied electric field when the oxide thickness is each $600[\AA],\;800[\AA]$ and $1000[\AA]$, respectively. We known that the leakage current is a little higher when the voltage as reverse bias contrast with forward bias in poly gate is applied. In order to experiment for AC properties is measured for capacitance characteristics. It is confirmed that the value of input capacitance have been a lot of influenced on $SiO_2$ thickness contrast with the value of output capacitance.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.395-398
• /
• 2004

High-linearity voltage-controlled current sources (VCCSs) circuits for wide voltage-controlled oscillator and automatic gun control were proposed. The VCCS consists of emitter follower for voltage input, two common-base amplifier which their emitter connected for current output, and current mirror which connected the two amplifier for large output current. The VCCS used only five transistors and a resistor without an extra bias circuit. Simulation results show that the VCCS has current output range from 0mA to 300mA over the control voltage range from 1V to 4.8V at supply voltage 5V. The linearity error of output current has less than $1.4\%$ over the current range from 0A to 300mA.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
• /
• 2002.02a
• /
• pp.109-110
• /
• 2002

The purpose of a superconductive DC/SFQ circuit is to produce a controlled number of picosecond single flux quantum pulses at the output when a slowly changing DC current is applied to the input. In this work, we have designed and simulated a DC/SFQ circuit based on Nb/Al$O_{x}$/Nb Josephson junction technology. From the simulation, we could obtain the margins for various circuit parameters. And also we have successfully operated a DC/SFQ circuit which was fabricated with the same design. The margin for the input bias current of the circuit was observed to be of $\pm$60%, which was very close to the simulated value.