• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.345-355
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• 2014

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.517-518
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• 2008

Highly integrated ISFETs require the monolithic implementation of ISFETs, CMOS electronics, and additional sensors on the same chip This paper presents novel packaging type of CMOS ISFET pH sensor using standard CMOS FET chip and extended sensing membrane which is separated from CMOS FET. This proposed packaging type will make it easy to fabricate CMOS ISFET pH sensors

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.679-682
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• 2003

Improvement in MOS fabrication technology have led to high-density high-performance integrated circuits with MOSFET channel lengths in the sub-micron range. For devices of the size, transistor characteristics become highly sensitive to effective channel length. We propose a new approach to extract the effective channel length of MOSFET by Capacitance-Voltage (C-V) method. Gate-to-Source, Drain capacitance ( $C_{gsd}$) are measured and the effective channel length can be extracted. In addition, compared to l/$\beta$ method and Terada method, which has been point out that it fails to extract the accurate effective channel length of the devices, we prove that our approach still works well for the devices with down to sub-micron regime.e.

• Proceedings of the Korean Environmental Health Society Conference
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• 2002.04a
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• pp.1.1-2
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• 2002

Ultimate objective of industrial hygiene is the prevention of health impairment that may result from exposure to chemicals at workplaces. This implies the definition of permissible levels of exposure, that is, levels that according to the present status of knowledge are estimated to cause no adverse health effects during the lifetime of the workers, and the regular assessment of the possible health risk associated with exposure by comparing the current or the integrated exposure with the permissible exposure limits. Workers in solvent thinner-using occupation environment might be highly exposed to VOCs(volatile organic compounds) because solvent thinner has been used extensively such as painting, spraying, degreasing, coating and so on in Korea. The purpose of this study was to recognize, evaluate and propose the alternative control the VOCs from solvent thinner-using workplace.

• Journal of Mechanical Science and Technology
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• v.16 no.2
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• pp.246-254
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• 2002

Recent primary concern for the design of high performance heat exchanger and highly integrated electronic equipments is to develop an active and creative technologies which enhance the heat transfer without obstructing the coolant flows. In this study, we found through the LDV measurement that the gaseous cavitation induced by ultrasonic vibration applied to the CO$_2$saturated water in the square cross-sectioned straight duct flow enhances the turbulence much more than the case of non-ultrasonic or normal ultrasonic conditions without gaseous cavitation does. We also found that gaseous cavitation can enhance effectively the turbulent heat transfer between the heating surfaces and coolants by destructing the viscous sublayer.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.4
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• pp.562-568
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• 2009

In this paper, using the periodic ground structure (PGS), highly miniaturized branch-line coupler and impedance transformer were realized on Si radio frequency integrated circuit (RFIC). The branch-line couple exhibited good RF performance from 41.75 to 50 GHz, and its size was $0.46{\times}0.55mm^2$, which is 37 % of conventional one. The impedance transformer exhibited good RF performance from 1 to 40GHz, and its size was $0.01mm^2$, which is 6.99 % of conventional one.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• Proceedings of the Optical Society of Korea Conference
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• 1991.06a
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• pp.190-193
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• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

• 한국신재생에너지학회:학술대회논문집
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• 2007.11a
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• pp.19-22
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• 2007

In this study, we investigated operating characteristics of natural gas fuel processor for polymer electrolyte membrane fuel cells (PEMFCs). The fuel processor consists of a natural gas reformer, a water-gas shift reactor, a heat-exchanger and a burner, in which the overall integrated volume is exactly(exceptionally) small, namely, about 10L except outer insulation. The producted hydrogen is $1Nm^3/hr$ and the maximum thermal efficiency is ${\sim}76%$(low heating value) at full operating load. A compact and highly efficient $1Nm^3/hr$ class natural gas fuel processor was developed at UNISON is an advantage for application in residential PEMFCs co-generation systems.

• The Korean Journal of Applied Statistics
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• v.23 no.2
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• pp.249-261
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• 2010

Long-term forecasting of seasonal time series is critical in many applications such as planning business strategies and resolving possible problems of a business company. Unlike the traditional approach that depends solely on dynamic models, Li and Hinich (2002) introduced a combination of stochastic dynamic modeling with filter bank approach for forecasting seasonal patterns using highly coherent(High-C) waveforms. We modify the filter selection and forecasting procedure on wavelet domain to be more feasible and compare the resulting predictor with one that obtained from the wavelet variance estimation method. An improvement over other seasonal pattern extraction and forecasting methods based on such as wavelet scalogram, Holt-Winters, and seasonal autoregressive integrated moving average(SARIMA) is shown in terms of the prediction error. The performance of the proposed method is illustrated by a simulation study and an application to the real stock price data.