• 전자공학회논문지A
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• 제33A권7호
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• pp.162-170
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• 1996

A breakdown model of gate oxides under constant current stresses is proposed. This model directly relates the oxide lifetime to the stress current density, and includes statistical nature of oxide breakdown using the concept of "effective oxide thinning". It is shown tha this model can reliably predict the TDDB characteristics for any current stress levels and oxide areas.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
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• pp.941-943
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• 1999

In this paper, the AC breakdown properties to investigate the electrical properties of gate oxide layer in MOSFET was studied. 5 inch arsenic epi-wafer is selected as an experimental specimen, the power MOSFET of a general MOS structure was made. In order to analyze the physical properties of the specimen, the SIMS(secondary ion mass spectroscopy) was used. As the experimental condition, the experiment al of the AC breakdown characteristics was performed when the thickness of gate oxide layer is $600[\AA]$ and $800[\AA]$, the resistivity is $1.2[\Omega{\cdot}cm]$, $1.5[\Omega{\cdot}cm]$ and $1.8[\Omega{\cdot}cm]$, and the diffusion time is 110[min] and 150[min] in temperature $30[^{\circ}C]{\sim}100[^{\circ}C]$. From the analysis result of the SIMS spectrum, it is confirmed that the dielectric strength is decreased by contribution of the impurities ad dition as increasing in thickness of the gate oxide layer in MOSFET.

• Transactions on Electrical and Electronic Materials
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• 제10권6호
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• pp.193-195
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• 2009

This paper aims to develop a low gate source voltage ($V_{gs}$) N-LDMOS element that is fully operational at a CMOS Logic Gate voltage (3.3 or 5 V) realized using the 0.35 μm BCDMOS process. The basic structure of the N-LDMOS element presented here has a Low $V_{gs}$ LDMOS structure to which the thickness of a logic gate oxide is applied. Additional modification has been carried out in order to obtain features of an improved breakdown voltage and a specific on resistance ($R_{sp}$). A N-LDMOS element can be developed with improved features of breakdown voltage and specific on resistance, which is an important criterion for power elements by means of using a proper structure and appropriate process modification. In this paper, the structure has been made to withstand the excessive electrical field on the drain side by applying the double gate oxide structure to the channel area, to improve the specific on resistance in addition to providing a sufficient breakdown voltage margin. It is shown that the resulting modified N-LDMOS structure with the feature of the specific on resistance is improved by 31%, and so it is expected that optimized power efficiencies and the size-effectiveness can be obtained.

• 한국정보통신학회논문지
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• 제17권2호
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• pp.372-377
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• 2013

DGMOSFET의 항복전압에 대하여 고찰하였으며 이를 위하여 포아송방정식의 분석학적 해 및 Fulop의 항복전압 조건을 사용하였다. DGMOSFET는 게이트단자의 전류제어능력 향상으로 단채널 효과를 감소시킬 수 있다는 장점이 있다. 그러나 단채널에서 나타나는 항복전압의 감소는 피할 수 없으므로 이에 대한 연구가 필요하다. 포아송방정식을 풀 때 사용하는 전하분포함수에 가우시안 함수를 적용함으로써 보다 실험값에 가깝게 해석하였으며 이때 이중게이트 MOSFET의 소자크기에 따라 항복전압의 변화를 관찰하였다. 본 연구의 전위모델에 대한 타당성은 이미 기존에 발표된 논문에서 입증하였으며 본 연구에서는 이 모델을 이용하여 항복전압을 분석할 것이다. DGMOSFET의 항복전압을 관찰한 결과, 채널길이가 감소할수록 그리고 도핑농도가 증가할수록 항복전압이 감소하는 것으로 나타났다. 또한 게이트산화막 두께 및 채널두께에 따라서 항복전압의 변화가 관찰되었다.

• 한국재료학회지
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• 제3권6호
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• pp.638-644
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• 1993

티타니움 폴리사이드 MOS(metal oxide semiconducter)캐퍼시타 구조에서 두께가 8nm인 게이트산화막의 절연파괴강도의 열화거동을 열처리조건 및 폴리실리콘막의 두께를 달리하여 조사했다. 티타니움 폴리사이드 게이트에서 게이트산화막의 전연피괴특성은 열처리 온도가 높을수록, 열처리시간이 길수록 많이 열화되어 실리사이드의 하부막인 잔류 폴리실리콘의 두께가 얇을수록 그 정도는 심해진다. 티타니움 실리사이드가 게이트산화막고 직접적인 접촉이 없더라도 게이트산화막의 신회성이 열화되는 것을 알 수 있었다. 실리사이드 형성후 열처리에 따른 게이트 산화막의 절연파괴특성열화는 티타니움 원자가 폴리실리콘을 통해 게이트산화막으로 확산되어 게이트산화막에서 티타니움의 고용량이 증가한 때문인 것이 SIMS분석 결과로부터 확인되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.44-48
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• 1999

In order to the investigate for the DC(forward-reverse) breakdown properties of gate oxide in MOSFET, we are manufactured the specimen as following. The resistivity is 1.2($\Omega$ $.$ cm), 1.5($\Omega$ $.$ cm) and 1.8($\Omega$ $.$ cm) when thickness is 600(${\AA}$), and the diffusion time is both 110[min] and 150[min] when thickness is 600[${\AA}$]. In DC dielectric strength due to the each resistivity, it is confirmed that almost of the leakage current and breakdown current is flowed through n+ source when positive bias is applied, but is flowed through P region when negative bias is applied. It is thought that the dielectric strength due to the diffusion time is the contribution as increasing of p region.

• 센서학회지
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• 제28권1호
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• pp.17-22
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• 2019

As CMOS technology scales down, reliability is becoming an important concern for VLSI designers. This paper analyzes gate-oxide breakdowns (i.e., the time-dependent dielectric-breakdown (TDDB) aging effect) as a reliability issue for combinational circuits with 45-nm technology. This paper shows simulation results for the noise margin, delay, and power using a single inverter-chain circuit, as well as the International Symposium on Circuits and Systems (ISCAS)'85 benchmark circuits. The delay and power variations in the presence of TDDB are also discussed in the paper. Finally, we propose a novel method to compensate for the logic failure due to dielectric breakdowns: We used a higher supply voltage and a negative ground voltage for the circuit. The proposed method was verified using the ISCAS'85 benchmark circuits.

• 한국산업정보학회논문지
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• 제17권3호
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• pp.27-34
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• 2012

This paper presents the impact of time dependent dielectric breakdown (TDDB, also called as gate oxide breakdown) failure on nanoscale digital CMOS Circuits. Recently, TDDB for ultra-thin gate oxides has been considered as one of the critical reliability issues which can lead to performance degradation or logic failures in nanoscale CMOS devices. Also, leakage power in the standby mode can be increased significantly. In this paper, TDDB aging effects on large CMOS digital circuits in the 45nm technology are analyzed. Simulation results show that TDDB effect on MOSFET circuits can result in more significant increase of power consumption compared to delay increase.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.200-204
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• 2012

This study has presented the analysis of breakdown voltage for a double-gate metal-oxide semiconductor field-effect transistor (MOSFET) based on the doping distribution of the Gaussian function. The double-gate MOSFET is a next generation transistor that shrinks the short channel effects of the nano-scaled CMOSFET. The degradation of breakdown voltage is a highly important short channel effect with threshold voltage roll-off and an increase in subthreshold swings. The analytical potential distribution derived from Poisson's equation and the Fulop's avalanche breakdown condition have been used to calculate the breakdown voltage of a double-gate MOSFET for the shape of the Gaussian doping distribution. This analytical potential model is in good agreement with the numerical model. Using this model, the breakdown voltage has been analyzed for channel length and doping concentration with parameters such as projected range and standard projected deviation of Gaussian function. As a result, since the breakdown voltage is greatly changed for the shape of the Gaussian function, the channel doping distribution of a double-gate MOSFET has to be carefully designed.

• 전기전자학회논문지
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• 제25권2호
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• pp.350-355
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• 2021

IGBT는 MOSFET과 BJT의 구조를 동시에 포함하고 있는 전력반도체 소자이며, MOSFET의 빠른 스위칭 속도와 BJT의 고 내압, 높은 전류내량 특성을 갖고 있다. GBT는 높은 항복전압, 낮은 V_CE-SAT, 빠른 스위칭 속도, 고 신뢰성의 이상적인 파워 반도체 소자의 요구사항을 목표로 하는 소자이다. 본 논문에서는 1,200V 급 Trench Gate Field Stop IGBT의 상단 공정 파라미터인 Gate oxide thickness, Trench Gate Width, P+ Emitter width를 변화시키면서 변화하는 Eoff, V_CE-SAT을 분석하였고, 이에 따른 최적의 상단 공정 파라미터를 제시하였다. Synopsys T-CAD Simulator를 통해 항복전압 1,470V와 V_CE-SAT 2.17V, Eon 0.361mJ, Eoff 1.152mJ의 전기적 특성을 갖는 IGBT 소자를 구현하였다.