• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.686-694
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• 2014

A power semiconductor device, usually used as a switch or rectifier, is very significant in the modern power industry. The power semiconductor, in terms of its physical properties, requires a high breakdown voltage to turn off, a low on-state resistance to reduce static loss, and a fast switching speed to reduce dynamic loss. Among those parameters, the breakdown voltage and on-state resistance rely on the doping concentration of the drift region in the power semiconductor, this effect can be more important for a higher voltage device. Although the low doping concentration in the drift region increases the breakdown voltage, the on-state resistance that is increased along with it makes the static loss characteristic deteriorate. On the other hand, although the high doping concentration in the drift region reduces on-state resistance, the breakdown voltage is decreased, which limits the scope of its applications. This addresses the fact that breakdown voltage and on-state resistance are in a trade-off relationship with a parameter of the doping concentration in the drift region. Such a trade-off relationship is a hindrance to the development of power semiconductor devices that have idealistic characteristics. In this study, a novel structure is proposed for the Insulated Gate Bipolar Transistor (IGBT) device that uses conductivity modulation, which makes it possible to increase the breakdown voltage without changing the on-state resistance through use of a P-floating layer. More specifically in the proposed IGBT structure, a P-floating layer was inserted into the drift region, which results in an alleviation of the trade-off relationship between the on-state resistance and the breakdown voltage. The increase of breakdown voltage in the proposed IGBT structure has been analyzed both theoretically and through simulations, and it is verified through measurement of actual samples.

• Journal of Electrical Engineering and Technology
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• v.7 no.4
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• pp.601-605
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• 2012

Insulated Gate Bipolar Transistors(IGBTs) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the onstate voltage drop should be lowered and the switching time should be shortened. However, there is trade-off between the breakdown voltage and the on-state voltage drop. The FLoatingIsland(FLI) structure can lower the on-state voltage drop without reducing breakdown voltage. In this paper, The FLI IGBT shows an on-state voltage drop that is 22.5% lower than the conventional IGBT, even though the breakdown voltages of each IGBT are almost identical.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.325-328
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• 2002

In this paper. we propose a floating resistor with positive and negative resistance operating at lower supply voltages. The circuit uses only two transistors between the supply voltages. which enable to operate it at low supply voltages. Moreover. the circuit uses fewer number of transistors compared to the reported work. The gate terminal is used in this circuit for the current addition/subraction at the terminals of resistor. The characteristic of the proposed circuit is verified using HSPICE for the power supply +/-1.5V.

• Journal of IKEEE
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• v.17 no.3
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• pp.365-370
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• 2013

Power MOSFET is developed in power savings, high efficiency, small size, high reliability, fast switching, and low noise. Power MOSFET can be used in high-speed switching transistors devices. Recently attention given to the motor and the application of various technologies. Power MOSFET is a voltage-driven approach switching device and designed to handle on large power, power supplies, converters, motor controllers. In this paper, the 400 V Planar type, and the trench type for realization of low on-resistance are designed. Trench Gate Power MOSFET Vth : 3.25 V BV : 484 V Ron : 0.0395 Ohm has been optimized.

• Journal of IKEEE
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• v.17 no.3
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• pp.360-364
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• 2013

The maximum breakdown voltage's characteristic within the Super Junction MOSFET structure comes from N-Drift and P-Pillar's charge balance. By developing P-Pillar from Planar MOSFET, it was confirmed that the breakdown voltage is improved through charge balance, and by setting the gate voltage at 10V, the characteristic comparisons of Planar MOSFET and Super Junction MOSFET are shown in picture 6. The results show that it had the same breakdown voltage as Planar MOSFET which increased temperature resistance by 87.4% at $.019{\Omega}cm^2$ which shows that by the temperature resistance increasing, the power module's power dissipation improved.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.2
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• pp.235-238
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• 2008

This paper explores 28 nm MOSFET design for LSTP(Low Standby Power) applications using TCAD(Technology Computer Aided Design) simulation. Simulated results show that the leakage current of the MOSFET is increasingly dominated by GIDL(Gate Induced Drain Leakage) instead of a subthreshold leakage as the Source/Drain extension doping increases. The GIDL current can be reduced by grading lateral abruptness of the drain at the expense of a higher Source/Drain series resistance. For 28 nm MOSFET suggested in ITRS, we have shown Source/Drain design becomes even more critical to meet both leakage current and performance requirement.

• Journal of Korea Foundry Society
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• v.20 no.6
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• pp.368-376
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• 2000

Rheology forming technology has been accepted as a new method for fabricating near net shaped products with lightweight aluminum alloys. The rheology forming process consists of reheating process of billet, billet handling, filling into the die cavity and solidification of rheology formed part. The rheology forming experiments are performed with two different die temperatures ($T_d$ = $200^{\circ}C$, $300^{\circ}C$) and orifice gate type. The filling behavior and various defects of Al-Si materials with wear resistance (A357, A390 and ALTHIX 86S) fabricated in rheology forming process are evaluated in terms of alloying elements and surface non-uniformity. Finally, the methods to obtain the rheology formed products with high quality are described by solutions for avoiding the surface and internal defects.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.613-614
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• 2006

In this paper, BSIM4's IIR(Intrinsic Input Resistance) model that has a difficulty to predict $Z_{11}$ exactly is investigated by analyzing S-parameter measurement. Then a BSIM4 macro model for 70nm RF MOSFETs is proposed. That model uses external effective gate resistance which is composed of R and parallel RC. Comparison between simulation results using proposed model and IIR model is shown. The proposed model shows a better agreement between measured and simulated results up to 20GHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.26-29
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• 1999

The I-V characteristics of the n-channel offset gated poly-Si TETs have been systematically investigated in order to analyse the effects of offset region. The on currents are reduced due to the series resistance by the offset length and there is no kink phenomenon in offset devices. The off currents of the offset gated TFTs are remarkably reduced to 10$^{-12}$ A independent of gate and drain voltage because the electric field is weakened by the increase of the depletion region width near the drain region. It is shown that the offset regions behave as a series resistance and reduce lateral and vertical electric field.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.8
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• pp.501-504
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• 2014

This paper was developed and described core-process to implement low on resistance which was the most important characteristics of SJ (super junction) MOSFET. Firstly, using process-simulation, SJ MOSFET optimal structure was set and developed its process flow chart by repeated simulation. Following process flow, gate level process was performed. And source and drain level process was similar to genral planar MOSFET, so the process was the same as the general planar MOSFET. And then to develop deep trench process which was main process of the whole process, after finishing photo mask process, we developed deep trench process. We expected that developed process was necessary to develop SJ MOSFET for automobile semiconductor.