• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.263-267
• /
• 2014

Super junction trench gate power MOSFETs have been receiving attention in terms of the trade-off between breakdown voltage and on-resistance. The vertical structure of super junction trench gate power MOSFETs allows the on-resistance to be reduced compared with conventional Trench Gate Power MOSFETs. The heat release of devices is also decreased with the reduction of on-resistance. In this paper, Lattice Temperature of two devices, Trench Gate Power MOSFET and Super junction trench gate power MOSFET, are compared in several temperature circumstance with the same Breakdown Voltage and Cell-pitch. The devices were designed by 100V Breakdown voltage and measured from 250K Lattice Temperature. We have tried to investigate how much temperature rise in the same condition. According as temperature gap between top of devices and bottom of devices, Super junction trench gate power MOSFET has a tendency to generate lower heat release than Trench Gate Power MOSFET. This means that Super junction trench gate power MOSFET is superior for wide-temperature range operation. When trench etching process is applied for making P-pillar region, trench angle factor is also important component. Depending on trench angle, characteristics of Super junction device are changed. In this paper, we focus temperature characteristic as changing trench angle factor. Consequently, Trench angle factor don't have a great effect on temperature change.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.7
• /
• pp.667-674
• /
• 2005

In this paper the gate overlap length of the LDMOST is optimized for obtaining longer device lifetime. The LDMOSI device with drift region is fabricated using the $0.25\;{\mu}m$ CMOS Process. The gate overlap lengths on drift region are $0.1\;{\mu}m,\;0.4\;{\mu}m\;0.8\;{\mu}m\;and\;1.1\;{\mu}m$, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with gate overlap length of $0.4\;{\mu}m$ showed the longest on-resistance lifetime, 0.02 years and breakdown voltage of 22 V and on-resistance of $23\;m\Omega{\cdot}mm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.389-389
• /
• 2010

In this paper, an investigation of the benefits of gate oxide for 8" the manufacturing of Trench MOSFETs and its impact on device performance is presented. Layout dimensions of trench power MOSFETs have been continuously reduced in order to decrease the specific on-resistance, maintaining equal vertical dimensions. We discuss experimental results for devices with a pitch size down fabricated with an unconventional gate trench topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are observed the trench gate oxidation by SEM.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.1
• /
• pp.27-31
• /
• 2004

Models and simulations of gate tunneling current for thinoxide MOSFETs and Double-Gate SOIs are discussed. A guideline in design of leaky MOS capacitors is proposed and resonant gate tunneling current in DG SOI simulated based on quantum-mechanicalmodels. Gate tunneling current in fully-depleted, double-gate SOI MOSFETs is characterized based on quantum-mechanical principles. The simulated $I_G-V_G$ of double-gate SOI has negative differential resistance like that of the resonant tunnel diodes.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08b
• /
• pp.1597-1599
• /
• 2007

In TFT-LCD, mura is a defect which degrades the display quality. The resistance difference between gate lines is the main cause of H-Block mura. Two methods could eliminate this defect. A thinner gate layer or gate fan-out pattern decrease mura level. H-Block mura has been reduced after implementing the new schemes.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.19 no.6
• /
• pp.9-15
• /
• 2005

In this research the discharge characteristics of logic gate of the discharge logic gate plasma display panel with the NOT-AND logic function newly designed was analyzed. As for this discharge logic gate a logical output is induced by controlling the voltage between the electrodes using the discharge path. From the experimental result the discharge characteristics of logic gate is influenced by the interrelation of the voltages appling two vertical electrodes. To in the application possibility to large screen PDP, the discharge characteristics by the line resistance of the electrode was evaluated In result it has been inferred that the influence which the drop of voltage by the line resistance of two vertical electrodes exerts on the discharge of the logic gate is minute. Through the experiment, the optimized values of the pulse voltages and the current limitation resistances of each electrode which composed the discharge logic gate were obtained and maximum operation margin of 49[V] was obtained.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.28 no.12
• /
• pp.116-123
• /
• 2014

In case of power electronics, th power loss and EMI noise of IGBT is different depends on a adopting technology with the same power rating. To reduce the EMI noise, we could increase the resistance of gate. But in this case, the power loss of IGBT is increased, In this paper, we simulated the power loss of IGBT with the speed profile of elevator by the changing IGBT type, the voltage between gate and emitter, the resistance of gate in converter and inverter for elevator. To optimize the power electronics with the satisfied life time, It is necessary that we calculate the power loss and the rise of temperature in IGBT with the adopting technology type, the resistence of gate, the voltage between gate and emitter.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.11
• /
• pp.49-54
• /
• 1990

In this paper, a simple model is presented for the gate-voltage dependence of the parasitic resistance in MOSFETs with the lightly-doped drain (LDD) structure. At the LDD region located under the gate electrode, an accumulation layer is formed due to the gate voltage. The parasitic resistance of the source side LDD in the channel is treated as a parallel combination of the resistance of the accumulation layer and that of the bulk LDD, which is approximated as a spreading resistance from the end of the channel inversion layer to the ${n^+}$/LDD junction boundary. Also the effects of doping gradients at the junction are discussed. As result of the model, the LDD resistance decreases with increasing the gate voltage at the linear regime, and increase quasi-linearly with the gate voltage at the saturation regime, considering th velocity saturation both in the channel and in the LDD region. The results are in good agreement with experimental data reported by others.

• Transactions on Electrical and Electronic Materials
• /
• v.17 no.5
• /
• pp.302-305
• /
• 2016

In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2012.05a
• /
• pp.67.1-67.1
• /
• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.