• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.2
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• pp.6-12
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• 1998

Thin film SOI(Silicon-on-insulator) device offer unique advantages such as reduction in short channel effects, improvement of subthreshold slope, higher mobility, latch-up free nature, and so on. But these devices exhibit floating-body effet such as current kink which inhibits the proper device operation. In this paper, the SOI NMOSFET with a T-type gate structure is proposed to solve the above problem. To simulate the proposed device with TSUPREM-4, the part of gate oxide was considered to be 30nm thicker than the normal gate oxide. The I-V characteristics were simulated with 2D MEDICI. Since part of gate oxide has different oxide thickness, the gate electric field strength is not same throughout the gate and hence the impact ionization current is reduced. The current kink effect will be reduced as the impact ionization current drop. The reduction of current kink effect for the proposed device structure were shown using MEDICI by the simulation of impact ionization current, I-V characteristics, and hole current distribution.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.897-900
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• 2005

RF linearity of double-gate MOSFETs is investigated using accurate two-dimensional simulations. The linearity has been analyzed using the Talyor series. Transconductance is dominant nonlinear source of CMOS. It is shown that DGMOSFET linearity can be improved by a careful optimization of channel thickness, gate oxide thickness, gate length, overlap length and channel doping concentration. The minimum $P_{IP3}$ data are compared in each case. It is shown that DG-MOSFET linearity can be improved by a careful optimization of channel thickness, gate oxide thickness, gate length, overlap length and channel doping concentration..

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.347-350
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• 2001

A typical Mold method is to form a gate electrode, a gate oxide, and emitter tip after fabrication of mold shape using wet-etching of Si substrate. In this study, however, new Mold method using a side wall space structure is used in order to make sharper emitter tip with a gate electrode. Using LPCVD(low pressure chemical vapor deposition), a gate oxide and electrode layer are formed on a Si substrate, and then BPSG(Boro phospher silicate glass) thin film is deposited. After, the BPSG thin film is flowed into a mold as high temperature in order to form a sharp mold structure. Next TiN thin film is deposited as a emitter tip substance. The unfinished device with a glass substrate is bonded by anodic bonding techniques to transfer the emitters to a glass substrate, and Si substrate is etched using KOH-deionized water solution. Finally, we made sharp field emitter array with gate electrode on the glass substrate.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.127-133
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• 1996

In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photoresist reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate form both sides of the main gate. The poly-Si channel layer below the offset oxide is protected form the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of oru new device is the offset region due to the offset oxide. our experimental reuslts show that the offset region, due to the photoresist reflow process, has been sucessfully obtained in order to fabricate the offset gated poly-Si TFTs. The maximum ON/OFF ratio occurs at the L$_{off}$ of 1.1${\mu}$m and exceeds 1X10$^{6}$.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.4
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• pp.208-212
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• 2004

In this paper, the characteristics of co-sputtered Ru-Zr metal alloy as gate electrode of MOS capacitors have been investigated. The atomic compositions of alloy were varied by using the combinations of relative sputtering power of Ru and .Zr. C-V and I-Vcharacteristics of MOS capacitors were measured to find the effective oxide thickness and work function. The alloy made of about 50% of Ru and 50% of Zr exhibited an adequate work function for nMOS. C-V and I-V measurements after 600 and $700^{\circ}C$ rapid thermal annealing were performed to prove the thermal and chemical stability of the Ru-Zr alloy film. Negligible changes in the accumulated capacitance and work function before and after annealing were observed. Sheet resistance of Ru-Zr alloy was lower than that of poly-silicon. It can be concluded that the Ru-Zr alloy can be a possible substitute for the poly-silicon used as a gate of nMOS.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.586-591
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• 2004

We studied the dependence of hot-tarrier-induced degradation characteristics on nitrogen concentration in NO(Nitrided-Oxide) gate of nMOS, under ac and dc stresses. The $\Delta$V$_{t}$ and $\Delta$G$_{m}$ dependence of nitrogen concentration were observed, We observed that device degradation was suppressed significantly when the nitrogen concentration in the gate was increased. Compared to $N_2$O oxynitride, NO oxynitride gate devices show a smaller sensitivity to ac stress frequency. Results suggest that the improved at-hot carrier immunity of the device with NO gate may be due to the significantly suppressed interface state generation and neutral trap generation during stress.ess.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.575-580
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• 2015

Asymmetric double gate(DG) MOSFET is a novel transistor to be able to reduce the short channel effects. This paper has analyzed a off current for conduction path of asymmetric DGMOSFET. The conduction path is a average distance from top gate the movement of carrier in channel happens, and a factor to change for oxide thickness of asymmetric DGMOSFET to be able to fabricate differently top and bottom gate oxide thickness, and influenced on off current for top gate voltage. As the conduction path is obtained and off current is calculated for top gate voltage, it is analyzed how conduction path influences on off current with parameters of oxide thickness and channel length. The analytical potential distribution of series form is derived from Poisson's equation to obtain off current. As a result, off current is greatly changed for conduction path, and we know threshold voltage and subthreshold swing are changed for this reasons.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.23-30
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• 2006

This paper describes the short-channel effect(SCE), corner effect of nano-scale MuGFETs(Multiple-Gate FETs) by three-dimensional simulation. We can extract the equivalent gate number of MuGFETs(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4) by threshold voltage model. Using the extracted gate number(n) we can calculate the natural length for each gate devices. We established a scaling theory for MuGFETs, which gives a optimization to avoid short channel effects for the device structure(silicon thickness, gate oxide thickness). It is observed that the comer effects decrease with the reduction of doping concentration and gate oxide thickness when the radius of curvature is larger than 17 % of the channel width.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.207.2-207.2
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• 2015

차세대 디스플레이 소자로서 TAOS TFT (transparent amorphous oxide semiconductor Thin Film Transistor)가 주목 받고 있다. 또한, 최근에는 값 비싼 전자 제품을 저렴하고 간단히 처분 할 수 있는 시스템으로 대신 하는 연구가 진행되고 있다. 그중, cellulose-fiber에 전기적 시스템을 포함시키는 e-paper에 대한 관심이 활발하다. cellulose fiber는 가볍고 깨지지 않으며 휘는 성질을 가지고 있다. 가격도 저렴하고 가공이여 용이하여 차세대 기판의 재료로서 주목받고 있다. 하지만, cellulose-fiber 위에는 고온의 열처리공정과 고품질 박막 성장이 어려워서 TFT 제작에 어려움을 겪고 있다. 이러한 문제를 해결하기 위해서 산화물 반도체를 이용하여 TFT를 제작한 사례가 보고되고 있다. 또한, 채널 물질 뿐만 아니라 cellulose fiber에도 다른 물질을 첨가하거나 증착하여 전기적 화학적 특성을 개선시킨 사례도 많이 보고되고 있다. 본 연구에서는 가장 저품질의 용지로 알려진 신문지와 A4용지를 gate dielectric을 이용하여서 a-IGZO TFT를 제작하였다. 하지만, cellulose fiber로 만들어진 TFT의 경우에는 고온의 열처리가 불가능 하다. 따라서 저온에서 높을 효율은 보이는 microwave energy를 이용하여 열처리를 진행하였다. 추가적으로 저품질의 종이의 특성을 개선시키기 위해서 high-k metal-oxide solution precursor를 첨가 하여 TFT의 특성을 개선시켰다. 결과적으로 cellulose fiber에 metal-oxide solution precursor을 첨가하는 공정과 micro wave를 조사하는 방법을 사용하여 100도 이하에서 cellulose fiber를 저렴하고 우수한 성능의 TFT를 제작에 성공하였다.