• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• Transactions on Electrical and Electronic Materials
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• v.3 no.1
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• pp.4-8
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• 2002

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.3
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• pp.233-237
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• 2002

A giga-bit DRAM(dynamic random access memory) technology with W/WNx/poly-Si dual gate electrode is presented in 7his papers. We fabricated $0.16\mu\textrm{m}$ CMOS using this technology and succeeded in suppressing short-channel effects. The saturation current of nMOS and surface-channel pMOS(SC-pMOS) with a $0.16\mu\textrm{m}$ gate was observed 330 $\mu\A/\mu\textrm{m}$ and 100 $\mu\A/\mu\textrm{m}$ respectively. The lower salutation current of SC-pMOS is due to the p-doped poly gate depletion. SC-pMOS shows good DIBL(dram-induced harrier lowering) and sub-threshold characteristics, and there was no boron penetration.

• Transactions on Electrical and Electronic Materials
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• v.14 no.1
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• pp.28-31
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• 2013

A volcano shaped gated Si-FEA (silicon field emitter array) was simply fabricated using sputtering as a gate electrode deposition and lift-off for the removal of the oxide mask, respectively. Due to the limited step coverage of well-controlled sputtering and the high aspect ratio in Si dry etch caused by high RF power, it was possible to obtain Si FEAs with a stable volcano shaped gate structure and to realize the restriction of gate leakage current in field emission characteristics. For 100 tip arrays and 625 tip arrays, gate leakage currents were restricted to less than 1% of the anode current in spite of the volcano-shaped gate structure. It was also possible to keep the emitters stable without any failure between the Si cathode and gate electrode in field emission for a long time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.25-28
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• 1999

Metal ferroelectric semiconductor Field Effect- Transistors(MFSFET) with various gate electrodes, that are aluminum, platinum and poly -Si, using LiNbO$_3$/Si(100) structures were fabricated and the properties of the FETs have been discussed. The drain current of the state of FET with Pt electrode was more than 3 orders of magnitude larger than the state current at the same gate voltage of 1.5 V, 7.rich means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about 10$^3$s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.104-104
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• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.7
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• pp.557-562
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• 2000

160nm thick amorphous Si and polycrystalline Si were each deposited on to 10nm thick SiO$_2$, Co monolayer and Co/Ti bilayer were sequentially evaporated to form Co-polycide. Then MOS capacitors were fabricated by BF$_2$ ion-implantation. The characteristics of the fabricated capacitor samples depending upon the drive-in annel conductions were measured to study the effects of thermal stability of CoSi$_2$and dopant redistribution on electrical properties of Co-polycide gates. Results for capacitors using Co/Ti bilayer and drive-in annealed at 80$0^{\circ}C$ for 20~40sec. showed excellent C-V characteristics of gate electrode.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.2
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• pp.110-118
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• 2002

Organic thin film transitors(OTFT) are of interest for use in broad area electronic applications. And recently organic electroluminescent devices(OELD) have been intensively investigated for using in full-color flat-panel display. We have fabricated inverted-staggered structure OTFTs at lower temperature using the fused-ring polycyclic aromatic hydrocarbon pentacene as the active eletronic material and photoacryl as the organic gate insulator. The field effect mobility is 0.039∼0.17 ㎠/Vs, on-off current ratio is 10$\^$6/, and threshold voltage is -7V. And here we report the study of driving emitting, Ir(ppy)$_3$, phosphorescent OELD with all organic thin film transistor and investigated its electrical characteristics. The OELD with a structure of ITO/TPD/8% Ir(ooy)$_3$ doped in BCP/BCP/Alq$_3$/Li:Al/Al and OTFT with a structure of inverted-stagged Al(gate electrode)/photoacry(gate insulator)/pentacene(p-type organic semiconductor)/ Au(source-drain electrode) were fabricated on the ITP patterned glass substrate. The electrical characteristics are turn-on voltage of -10V, and maximum luminance of about 90 cd/㎡. Device characteristics were quite different with that of only OELD.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.10
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• pp.668-672
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• 2014

Carbon nanotubes(CNT) has chemical stability and great sensitivity characteristics. In particular, the gas sensor required characteristics such as rapid, selectivity and sensitivity sensor. Therefore, CNT are ideal materials to gas sensor. So, we fabricated the NOx gas sensors of MOS-FET type using the MWCNT (multi-walled carbon nanotube). The fabricated sensor was used to detect the NOx gas for the variation of $V_{gs}$(gate-source voltage) and electrode changed electrode spacing=30, 60, 90[${\mu}m$]. The gas sensor absorbed with the NOx gas molecules showed the decrease of resistance, and the sensitivity of sensor was increased by magnification of electrode spacing. Furthermore, when the voltage($V_{gs}$) was applied to the gas sensor, the decrease in resistance was increased. On the other hand, the sensor sensitivity for the injection of NOx gas was the highest value at the electrode spacing $90[{\mu}m]$. We also obtained the adsorption energy($U_a$) using the Arrhenius plots by the reduction of resistance due to the voltage variations. As a result, we obtained that the adsorption energy was increased with the increment of the applied voltages.

• Applied Chemistry for Engineering
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• v.20 no.1
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• pp.99-103
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• 2009

HBr and $O_2$ in $Cl_2$ gas ambient for the high density plasma gate etching has been used to increase the performance of gate electrode in semiconductor devices. When an un-doped amorphous silicon layer was used for a gate electrode material, the notching profile was observed at the outer sidewall foot of the outermost line. This phenomenon can be explained by the electron shading effect: i.e., electrons are captured at the photoresist sidewall while ions pass through the photoresist sidewall and reach the oxide surface at a narrowly spaced pattern during the over etch step. The potential distribution between gate lines deflects the ions trajectory toward the gate sidewall. In this study, an appropriate mechanism was proposed to explain the occurrence of notching in the gate electrode of un-doped amorphous silicon.