• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.125-135
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• 2009

An analytical 2-dimensional model to explain the small signal and noise properties of an AlGaN/GaN modulation doped field effect transistor has been developed. The model is based on the solution of two-dimensional Poisson's equation. The developed model explains the influence of Noise in ohmic region (Johnson noise or Thermal noise) as well as in saturated region (spontaneous generation of dipole layers in the saturated region). Small signal parameters are obtained and are used to calculate the different noise parameters. All the results have been compared with the experimental data and show an excellent agreement and the validity of our model.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.107.1-107
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• 2001

In this paper, a digital signal processing circuit for Position Sensitive Detectors(PSDs) is introduced to substitute the conventional analog signal processing circuit and to compensate disadvantages of the PSD. In general, the analog circuits have the problems such as noise accumulation, sensitivity for environmental changes, and high cost for manufacturing. Moreover, the intrinsic nonlinearity problem of the PSD makes it hard to measure the position accurately because it is difficult to be overcome the problem by using the conventional analog circuits, which can be solved by using the digital signal processing circuit. The circuit is implemented by using a Field Programmable Gate Array (FPGA). The Pulse Amplitude Modulation(PAM) method is used for reducing the environmental noise effect, and a linear interpolation logic is used to compensate the ...

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2594-2596
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• 1999

Recently, white good market has interest with inverter product, which has merit to on/off type with respect to energy saving and noise. But, inverter product's cost is rising, because of adding inverter circuit component. To reduce cost, inverter gate drive trend is using HVIC which needs only single voltage. Also using HVIC, designer can compact PCB'size. This paper shows application technique and key point of designing HVIC

• 센서학회지
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• 제28권1호
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• pp.17-22
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• 2019

As CMOS technology scales down, reliability is becoming an important concern for VLSI designers. This paper analyzes gate-oxide breakdowns (i.e., the time-dependent dielectric-breakdown (TDDB) aging effect) as a reliability issue for combinational circuits with 45-nm technology. This paper shows simulation results for the noise margin, delay, and power using a single inverter-chain circuit, as well as the International Symposium on Circuits and Systems (ISCAS)'85 benchmark circuits. The delay and power variations in the presence of TDDB are also discussed in the paper. Finally, we propose a novel method to compensate for the logic failure due to dielectric breakdowns: We used a higher supply voltage and a negative ground voltage for the circuit. The proposed method was verified using the ISCAS'85 benchmark circuits.

• 대한전자공학회논문지SD
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• 제45권10호
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• pp.7-14
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• 2008

본 논문에서는 $1.0{\mu}m$ BCD 650V 공정을 이용하여 향상된 잡음 내성과 높은 전류 구동 능력을 갖는 고전압 구동 IC를 설계하였다. 설계된 고전압 구동 IC는 500kHz의 고속 동작이 가능하고, 입력 전압의 범위가 최대 650V이다. 설계된 IC에 내장된 상단 레벨 쉬프터는 잡음 보호회로와 슈미트 트리거를 포함하고 있으며 최대 50V/ns의 높은 dv/dt 잡음 내성을 가지고 있다. 또한 설계된 숏-펄스 생성회로가 있는 상단 레벨 쉬프터의 전력 소모는 기존 회로 대비 40% 이상 감소하였다. 이외에도 상 하단 파워 스위치의 동시 도통을 방지하는 보호회로와 구동부의 전원 전압을 감지하는 UVLO(Under Voltage Lock-Out) 회로를 내장하여 시스템의 안정도를 향상시켰다. 설계된 고전압 구동 IC의 특성 검증에는 Cadence사의 spectre 및 PSpice를 이용하였다.

• ETRI Journal
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• 제27권5호
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• pp.628-634
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• 2005

From AC analysis results utilizing a 2-dimensional device simulator, we extracted an AC-equivalent circuit of a grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.

• 한국통신학회논문지
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• 제24권10A호
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• pp.1579-1587
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• 1999

게이트 길이가 $0.2\mu\textrm{m}$인 P-HEMT에 대하여 드레인 바이어스 전류의 변화 및 게이트 폭에 대해 스케일링이 가능한 잡음모델을 제안하였다. 본 논문에서는 S-파라미터를 정확히 예측하기 위하여 $\tau$를 제외한 intrinsic 파라미터는 offset를 도입하여 정규화 한 후 스케일링을 하였다. 드레인 포화전류에 대한 드레인 전류의 비율과 게이트 폭을 변수로 하는 소신호 모델 파라미터의 맞춤함수를 구하였다. 또한, 잡음 파라미터를 정확히 예측하기 위하여 진성저항 잡음 온도 $\textrm{T}_{g}$, 게이트 단 전류 잡음원 등가잡음 컨덕턴스 $\textrm{G}_{ni}$, 드레인 단 전류와 게이트 폭에 거의 관계없으며 이의 평균값은 주변온도와 유사한 값으로 $\textrm{G}_{ni}$는 회로 특성에 영향을 미치지 않을 정도로 작은 값으로 추출되었다. 그러므로, $\textrm{G}_{no}$만을 잡음 모델정수로 하는 잡음모델과 $\textrm{T}_{g}$, $\textrm{G}_{ni}$, $\textrm{G}_{no}$를 잡음 모델정수로 하는 잡음모델을 측정값과 비교하여 본 결과 Gno만을 갖는 잡음모델도 측정된 잡음 파라미터와 잘 일치하였다. 따라서, 모델 정수추출이 간단한 $\textrm{G}_{no}$만을 갖는 잡음모델은 게이트 폭과 바이어스 전류에 대해 스케일링이 가능한 실용적인 잡음모델임을 확인하였다.

• 정보통신설비학회논문지
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• 제9권4호
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• pp.141-146
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• 2010

In this paper, bandgap reference PTAT(Proportional to Absolute Temperature) circuit and flexible gain control of LNA(Low Noise Amplifier) which is usable in Zigbee system of 2.4GHz band are designed by TSMC $0.18{\mu}m$ CMOS library. PTAT bandgap reference circuit is proposed to minimize the instability of CMOS circuit which may be unstable in temperature changes. This circuit is designed such that output voltage remains within 1.3V even when the temperature varies from $-40^{\circ}C$ to $-50^{\circ}C$ when applied to the gate bias voltage of LNA. In addition, the LNA is designed to be operated on 2.4GHz which is applicable to Zigbee system and able to select gains by changing output impedance using 4 NMOS operated switches. The simulation result shows that achieved gain is 14.3~17.6dB and NF (Noise Figure) 1.008~1.032dB.

• Carbon letters
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• 제13권1호
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• pp.17-22
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• 2012

Currently, graphene is a topic of very active research in fields from science to potential applications. For various radio-frequency (RF) circuit applications including low-noise amplifiers, the unique ambipolar nature of graphene field-effect transistors can be utilized for high-performance frequency multipliers, mixers and high-speed radiometers. Potential integration of graphene on Silicon substrates with complementary metal-oxide-semiconductor compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene metal-oxide-semiconductor field-effect transistors to minimize parasitics and improve gate modulation efficiency in the channel. In this paper, we highlight recent progress in graphene materials, devices, and circuits for RF applications. For passive RF applications, we show its transparent electromagnetic shielding in Ku-band and transparent antenna, where its success depends on quality of materials. We also attempt to discuss future applications and challenges of graphene.

• 한국자동차공학회논문집
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• 제16권1호
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• pp.1-7
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• 2008

This paper presents electromagnetic interference(EMI) suppression method applied on the direct current(DC) motor driver for power tail gate control. EMI noise is generated by the fast switching of power devices connected to electric loads. It has become a matter of concern because of the vast increase in the number and sophistication of electronic system in automotive environment. The proposed EMI reduction method is based on the principle of reducing the transient speed of power devices by changing the parameters of the driver circuit related to the power MOSFET. In this paper, power losses were calculated by loss equations and thermal simulation was used to evaluate the effect on printed circuit board. Based on these results, the DC motor driver was fabricated and tested. The proposed method can help to design a DC motor driver which allows it to obtain an acceptable compromise between power losses and EMI.