• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.127-130
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• 2000

This paper proposes a low-Power DDC(Digital Down Converters) architecture for IF(Intermediate frequency) signal processing. It is shown that concept of conventional interpolated FIR filters can be expanded to IIR filters for DDC applications. Also in the paper, power dissipations for the proposed architecture and conventional ones are estimated.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1627-1633
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• 2018

A constant voltage AC-DC converter based on digital assistant technology is proposed in this paper, which has rapid dynamic response capability. The converter operates in the PFM (Pulse Frequency Modulation) mode. According to the load state, the compensation current produced by the digital compensation module was injected into the CS pin to adjust the switching pulse width dynamically and improve the dynamic response. The control chip is implemented based on NEC $1{\mu}m$ 5V/40V HVCMOS process. A 5V/1.2A prototype has been built to verify the proposed control method. When the load jumps from idle to heavy, the undershoot time is only 7.4ms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.963-969
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• 2008

This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.181-182
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• 2008

In this paper, an cost-effective system architecture is proposed to implement digital predistortion scheme for linearizing the PA amplifing TDD wideband signal. To make digital predistorted signal for compensating nonlinearity of PA, a dedicated ADC and a frequency-down converter are necessary. Proposed scheme is based on the TDD feature that the RF receiver frontend is idle state during the downlink signal processing time and utilize them to make the digital predistorted signal for PA.

• ETRI Journal
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• v.46 no.2
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• pp.238-249
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• 2024

Equivalent-time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down-conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in-phase/quadrature gain imbalance instead of requiring a high-speed analog-to-digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent-time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent-time sampling using DDC.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.29-34
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• 2007

It is important to analyse the frequency spectrum for the measurement of modulated signal, distortion, and noise. The frequency spectrum analysis is performed by the execution of Radix-2 DIT DFT i.e. FFT algorithm. The discrete input signal converted by A/D converter from the input signal in time domain is mathematically transformed to the frequency spectrum by FFT algorithm. In this study, we design the digital spectrum analyser by the hardware based on the TMS320F2812 DSP and AD9244 converter, and by the software based on the C28x S/W modules. We can timely analyse the frequency spectrum in mobile communication system by the digital frequency analyser based on the high performance DSP and S/W modules. This real-time analysing capability is the important performance in the internet-based mobile communication server system.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.69-72
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• 2000

This paper shows the more improved design of MRI receiver compared to conventional one based on Elscint Spectrometer. At first, the low-cost ADC is 16 bits, 3MHz sampling A/D converter Comparing to conventional one with signal bits of 14 bits, this device with those of 16 bits helps getting Improved the image resolution improved. If frequency is designed centering around 7.6 MHz to be satisfied in 10 MHz of maximum input bandwidth of ADC. For 1st demodulation, fixed IF is used for the purpose of the implementing multi nuclei system. Control parts & partial digital parts are integrated on one chip(FPGA). In DDC(Digital Down Converter), we got required bandwidth of LPF by controlling its decimation rate. With above considerations, we designed optimal receiver for high resolution imaging to be implemented through PC interface & experimental test of receiver of MRI after receiver's fabrication.

• ETRI Journal
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• v.32 no.1
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• pp.154-156
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• 2010

Oscillation-based testing of analog-to-digital converters represents a viable option for low-cost built-in self-testing in mixed-signal design. While numerous papers have addressed implementation issues, little attention has been paid to the measurement accuracy. In this letter, we highlight an inherent measurement uncertainty which has to be considered when deriving the parameters from the oscillation frequency.

• Journal of IKEEE
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• v.16 no.4
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• pp.322-327
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• 2012

In this paper, a digital phase-locked loop(Digital-PLL) circuit with a new phase-to-digital converter(P2D) is described. The proposed digital PLL is composed a P2D, a digital loop filter(DLF), and a digitally controlled oscillator(DCO). The P2D generates a digital code for a phase error. The proposed P2D used a binary phase frequency detector(BPFD) and a counter in place of a time-to-digital converter(TDC) for simple structure, compact area and low power consumption. The proposed circuit was designed with CMOS 0.18um process. The simulation shows the circuit operates with the 1.0 to 2.2GHz with the power consumption of 16.2mW at 1.65GHz and the circuit occupies the chip area of $0.096mm^2$.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.