A Low-power Digital Down Converter Architecture Using Interpolated IIR Filters

Interpolated IIR 필터를 사용한 저전력 디지털 다운 컨버터 아키텍처

This paper proposes a low-Power DDC(Digital Down Converters) architecture for IF(Intermediate frequency) signal processing. It is shown that concept of conventional interpolated FIR filters can be expanded to IIR filters for DDC applications. Also in the paper, power dissipations for the proposed architecture and conventional ones are estimated.