• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.341-344
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• 2002

This paper is proposed a 8-bit analog to digital converter for CMOS image sensor. A analog to digital converter for CMOS image sensor is required function to control gain. Frequency divider is used In control gain in this proposed analog to digital converter. At 3.3 Volt power supply, total static power dissipation is 8㎽ and programmable gain control range is 30㏈. Newly suggested analog to digital converter is designed by 0.35um 2-poly 4-metal CMOS technology.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.273-276
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• 2003

In this paper, we designed and made up/down converter (UDC) for using W-CDMA digital pre-distortion system which is one of the efficiency enhancement techniques. UDC is required that frequency up(baseband to RF) and down(RF to baseband) of information signals. The focus of the design and PCB layout is to satisfy the linearity of the UDC. We tested that UDC was satisfied specification which is based on 3GPP base stations and repeaters. The ACLR results which are -51.84dBc(Up Converter) and -55.0dBc(Down Converter) at upper 5 MHz offset from center-frequency show that UDC satisfy the 3GPP specification with superior linearity data.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.131-135
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• 1991

A quantization error model is suggested for analog to frequency(A/F) converter in strapdown inertial navigation system(SDINS),which is characterized by some white noise exciting the state variables. Also, effects on the performance of SDINS by analog to digital(A/D) converter and A/F converter are analyzed and compared via covariance simulation. As a result, A/F converter turns out to be superior to the A/D converter with respect to the induced navigation error and the difficulty in circuit realization. The quantization error model developed in this paper appears to be useful for optimal filter design.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.618-621
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• 1999

With the advent of the high-speed microprocessor and DSP, the possibility of executing a control strategy in digital domain has become a reality. By the use of the DSP and microprocessor controller, many high power drive system may be enhanced resulting in the improved robustness to EMI, the ability to communicate the operating conditions and the ease of adjusting the control parameters. But, the digital controller using DSP or microprocessor is not applied in the high frequency switching power supplies, especially full bridge DC/DC converter. So, this paper presents the method and realization of designing a digital-to-phase shift PWM circuit for full digital controlled full bridge DC/DC converter with zero voltage switching. The operating principles, simulation and experimental results will be presented.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.12
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• pp.2000-2007
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• 2016

Generally, in order to implement the CRM(Critical Conduction Mode), the analog controller is used rather than a digital controller because the control is simple and uses less power. However, according to the semiconductor technology development and various user needs, digital control system based on a DSP is on the rise. Therefore, in this paper, the CRM bridgeless PFC converter based on a digital control is proposed. It is necessary to detect the inductor current when it reaches zero and peak value, for calculating the on time and off time by using the current information. However, in this paper, the on-time and off-time are calculated by using the proposed algorithm without any current information. If the switching-times are calculated through the steady-state analysis of the converter, they do not reflect transient status such as starting-up. Therefore, the calculated frequency is out of range, and the transient current is generated. In order to solve these problems, limitation method of the on-time and off-time is used, and the limitation values are varied according to the voltage reference. In addition, in steady state, depending on the switching frequency, the inductance is varied because of the resonance between the inductor and the parasitic capacitance of the switching elements. In order to solve the problem, inductance are measured depending on the switching frequency. The measured inductance are used to calculate the switching time for preventing the transient current. Simulation and experimental results are presented to verify the proposed method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.145-151
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• 2013

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.10
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• pp.1181-1187
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• 2014

In this paper, we implemented polar transmitt converter based on software for next generation digital wireless communication system. The implemented converter converted from rectangular to polar by CORDIC algorithm, and be made up of sweep for DDS output frequency using software control. The implemented converter shows can frequency control up to 1.16GHz within DDS frequency control range by software control. it means that transmitter can be control of varied blocks such as gain, phase, output and etc.. The implemented converter can be applied digital wireless communication system based on SDR.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.586-589
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• 2003

Repeater is developed. Based on the systems The up-converter of the WCDMA Digital Optic pecifications, the structure of the up-converter is accomplished and its block diagram is drawn. The up-converter is implemented according to these block diagrams. Subsequently the low pass filter, the automatic level controlled attenuator, the frequency synthesizer and other components for the up-converter are designed and implemented, and a main board to integrate these modules is also manufactured. To reduce the noise floor of system and suppress the RF spurious noise, a PCB layout is performed carefully. For each module consisting of the up-converter and the entire system, the performance tests are accomplished to check the performance about the specifications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.258-264
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• 2011

In this paper, we designed a frequency synthesizer with a low phase noise and fast lock time and excellent spurious characteristics using the offset-PLL(Phase Locked Loop) that is used in GSM(Global System for Mobile communications). The proposed frequency synthesizer has low phase noise using three times down conversion and third offset frequency of this synthesizer is created by DDS(Direct Digital Synthesizer) to have high frequency resolution. Also, this synthesizer has fast switching speed using DAC(Digital to Analog Converter). but phase noise degraded due to DAC. we improved performance using the DAC noise filter.

• ETRI Journal
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• v.33 no.3
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• pp.366-373
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• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.