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http://dx.doi.org/10.5573/JSTS.2013.13.2.145

A Low Power, Small Area Cyclic Time-to-Digital Converter in All-Digital PLL for DVB-S2 Application  

Kim, Hongjin (College of Information and Communication Engineering, Sungkyunkwan University)
Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.13, no.2, 2013 , pp. 145-151 More about this Journal
Abstract
In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.
Keywords
Cyclic; time-to-digital converter (TDC); phase-interpolator; time amplifier; all-digital phase-locked loop (ADPLL);
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