References
- R. B. Staszewski, P. T. Balsara, "Phase-domain alldigital phase-locked loop," IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 52, no. 3, pp. 159-163, Mar. 2005. https://doi.org/10.1109/TCSII.2004.842067
- P. Dudek, S. Szczepanski, J. V. Hatfield, "A highresolution CMOS time-to-digital converter utilizing a Vernier delay line," IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 240-247, Feb. 2000. https://doi.org/10.1109/4.823449
- Minjae Lee, A. A. Abidi, "A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue," IEEE J. Solid-State Circuits, vol. 43, no 4, pp. 769-777, Apr. 2008. https://doi.org/10.1109/JSSC.2008.917405
- S. Henzler, S. Koepp, D. Lorenz, W. Kamp, R. Kuenemund, D. Schmitt-Landsiedel, "A Local Passive Time Interpolator Concept for Variation- Tolerant High-Resolution Time-to-Digital Conversion," IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1666-1676, Jul. 2008. https://doi.org/10.1109/JSSC.2008.922712
- R. Tonietto, E. Zuffetti, R. Castello, I. Bietti, "A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter," in Proc. 32nd European Solid-State Circuits Conf. (ESSCIRC), 2006, pp. 150-153.
- Minjae Lee, M. E. Heidari, A. A. Abidi, "A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse-Fine Time-to-Digital Converter With Subpicosecond Resolution," IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2808-2816, Oct. 2009. https://doi.org/10.1109/JSSC.2009.2028753
- L. Vercesi, A. Liscidini, and R. Castello, "Two-Dimensions Vernier Time-to-Digital Converter," IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1504-1512, Aug. 2010. https://doi.org/10.1109/JSSC.2010.2047435
Cited by
- The Design of a 0.15 ps High Resolution Time-to-Digital Converter vol.15, pp.3, 2015, https://doi.org/10.5573/JSTS.2015.15.3.334
- A Study on the Noise Improvement of All Digital Phase-Locked Loop Using Time-to-Digital Converter vol.52, pp.2, 2015, https://doi.org/10.5573/ieie.2015.52.2.195