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http://dx.doi.org/10.5515/KJKIEES.2011.22.2.258

Design and Fabrication of a Offset-PLL with DAC  

Lim, Ju-Hyun (Samsung Thales Co., Ltd.)
Song, Sung-Chan (Samsung Thales Co., Ltd.)
Publication Information
The Journal of Korean Institute of Electromagnetic Engineering and Science / v.22, no.2, 2011 , pp. 258-264 More about this Journal
Abstract
In this paper, we designed a frequency synthesizer with a low phase noise and fast lock time and excellent spurious characteristics using the offset-PLL(Phase Locked Loop) that is used in GSM(Global System for Mobile communications). The proposed frequency synthesizer has low phase noise using three times down conversion and third offset frequency of this synthesizer is created by DDS(Direct Digital Synthesizer) to have high frequency resolution. Also, this synthesizer has fast switching speed using DAC(Digital to Analog Converter). but phase noise degraded due to DAC. we improved performance using the DAC noise filter.
Keywords
Offset-PLL; DDS; DAC; Frequency Synthesizer; Lock Time;
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