• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2005.11a
• /
• pp.137-140
• /
• 2005

A frequency synthesizer of 10 GHz $\sim$ 11 GHz for FMCW radar is designed and implemented by the form of indirect frequency synthesizer of a single loop structure. The synthesizer uses a high speed digital PLL chip. It is difficult to divide directly by using a program counter of PLL chip because the output frequency of VCO is 10 GHz $\sim$ 11 GHz, so we lower the frequency to 625 MHz $\sim$ 687.5 MHz by using a prescaler, and then divide the frequency by the program counter. The output frequency sweep of VCO from 10 GHz to 11 GHz is measured.

• Proceedings of the Korean Society of Marine Engineers Conference
• /
• 2005.11a
• /
• pp.208-209
• /
• 2005

A frequency synthesizer of 10 GHz ${\sim}$ 11 GHz for FMCW radar is designed and implemented by the form of indirect frequency synthesizer of a single loop structure. The synthesizer uses a high speed digital PLL chip. It is difficult to divide directly by using a program counter of PLL chip because the output frequency of VCO is 10 GHz ${\sim}$ 11 GHz, so we lower the frequency to 625 MHz ${\sim}$ 687.5 MHz by using a prescaler, and then divide the frequency by the program counter. The output frequency sweep of VCO from 10 GHz to 11 GHz is measured.

• Proceedings of the KIEE Conference
• /
• 2007.04a
• /
• pp.286-288
• /
• 2007

In this paper, the fast locking PLL Frequency Synthesizer with low phase noise in a 0.18um CMOS process is presented. Its main application IS for the 915MHz ISM band wireless transponder upon the CPFSK (Continuous Phase Frequency Shift Keying) modulation scheme. Frequency synthesizer, which in this paper, is designed based on self-biased techniques and is independent with processing technology when damping factor and bandwidth fixed to most important parameters as operating frequency ratio, broad frequency range, and input phase offset cancellation. The proposed frequecy synthesizer, which is fully-integrated and is in 320M $^{\sim}$ 960MHz of the frequency range with 10MHz of frequency resolution. And its is implemented based on integer-N architecture. Its power consumption is 50mW at 1.8V of supply voltage and core area is $540{\mu}m$ ${\times}$ $450{\mu}m$. The measured phase noises are -117.92dBc/Hz at 10MHz offset, with low settling time less than $3.3{\mu}s$.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.14 no.5
• /
• pp.818-824
• /
• 2011

In this paper, we proposed a phase noise model of a frequency synthesizer for a radar system. Especially, it was proposed a phase noise model in a DAS(Direct Analog Synthesizer) and a frequency up converter system using Leeson's model. The proposed phase noise model was derived from the measurement data of model 1 and evaluated by adapting to model 2 and model 3 frequency synthesizers. The prediction phase noise by modeling was totally matched to the measured data and the effective analysis of the phase noise was done in a frequency synthesizer and a frequency converter of radar system.

• Journal of Advanced Marine Engineering and Technology
• /
• v.30 no.3
• /
• pp.444-448
• /
• 2006

In this paper, a frequency synthesizer for X-band FMCW radars is proposed. Some X-band FMCW radars have been used as a level sensor for tanker ship and the resolution of the level sensor may be mainly depend on linearity of frequency sweep. For a linear frequency sweep. the proposed synthesizer employs a phase-locked loop using prescalars and a high speed digital PLL chip. The measured results show that the linear frequency sweep range is from 10 GHz to 11 GHz and the output power of the synthesizer is minium 7 dBm. and the phase noise is about -80 dBc/Hz at 100 KHz offset from 11 GHz.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.2 no.1
• /
• pp.41-48
• /
• 2002

This paper presents a 18-mW, 2.5-㎓ fractional-N frequency synthesizer with l-bit $4^{th}$-order interpolative delta-sigma ($\Delta{\;}$\sum$)modulator to suppress fractional spurious tones while reducing in-band phase noise. A fractional-N frequency synthesizer with a quadruple prescaler has been designed and implemented in a $0.5-\mu\textrm{m}$ 15-GHz $f_t$ BiCMOS. Synthesizing 2.1 GHzwith less than 200 Hz resolution, it exhibits an in-band phase noise of less than -85 dBc/Hz at 1 KHz offset frequency with a reference spur of -85 dBc and no fractional spurs. The synthesizer also shows phase noise of -139 dBc/Hz at an offset frequency of 1.2 MHz from a 2.1GHz center frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.05a
• /
• pp.197-200
• /
• 2001

Recently, Switching time is the principal factor in a design of frerquency synthesizer for Spread-Spectrum Communications. fast switching frequency synthesizer is important to improve the channel efficiency in a Frequency Hopping Spread Spectrum (FH-SS) tranceiver. In this paper, we design the frequency synthesizer with fast switching time as fast as 1${\mu}\textrm{s}$. In frequency synthesizer design, we use the interpolated PLL method inserted memory Look-up table of DDS to reduce switching time, and have result of improved channel efficiency about 20% by applying to FH-SS Transceiver.

• Proceedings of the KIEE Conference
• /
• 2007.10a
• /
• pp.191-192
• /
• 2007

This paper presents a 900MHz fractional-N frequency synthesizer for radio frequency identification (RFID) reader using $0.18{\mu}m$ standard CMOS process. The IC meets the EPC Class-1 Generation-2 and ISO-18000 Type-C standards. To minimize VCO pulling, the 900MHz VCO is generated by a 1.8GHz VCO followed by a frequency divider. The settling time of the synthesizer is less than $20{\mu}m$. The frequency synthesizer achieves the phase noise of -105.6dBc/Hz at 200kHz offset. The frequency synthesizer occupies an area of $1.8{\times}0.99mm^2$, and dissipates 8mA from a low supply voltage of 1.8V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.2
• /
• pp.258-264
• /
• 2011

In this paper, we designed a frequency synthesizer with a low phase noise and fast lock time and excellent spurious characteristics using the offset-PLL(Phase Locked Loop) that is used in GSM(Global System for Mobile communications). The proposed frequency synthesizer has low phase noise using three times down conversion and third offset frequency of this synthesizer is created by DDS(Direct Digital Synthesizer) to have high frequency resolution. Also, this synthesizer has fast switching speed using DAC(Digital to Analog Converter). but phase noise degraded due to DAC. we improved performance using the DAC noise filter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.12
• /
• pp.1251-1257
• /
• 2014

In this paper, a 6~13 GHz ultra high speed frequency synthesizer having minimum 30 kHz step size and minimum 500 ns frequency settling time is proposed. In order to obtain fast settling time, fine resolution, and good phase noise performance, wideband output frequencies were synthesized based on DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology. The phase noise performance of wideband frequency synthesizer was estimated by the superposition theory and its results were compared with measured ones. The measured frequency settling time was below 500 ns, phase noise was below -106 dBc @ 10 kHz at 13 GHz, and frequency accuracy was measured below ${\pm}2kHz$.