• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.1-6
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• 2004

For MOSFET devices with nanometer range gate length, accurate extraction of effective gate length is highly important because transistor characteristics become very sensitive to effective channel length. In this paper, we propose a new approach to extract the effective channel length of nanometer range MOSFET by Capacitance Voltage(C-V) method. The effective channel length is extracted using gate to source/drain capacitance( $C_{gsd}$). It is shown that 1/$\beta$ method, Terada method and other C-V method are inadequate to extract the accurate effective channel length. Therefore, the proposed method is highly effective for extraction of effective channel length of 100nm CMOSFETs.s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.1-8
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• 2002

C- V method is a means to determine the effective channel length for miniaturized MOSFET's. This method achieves L$_{eff}$ by extracting a unique channel length independent extrinsic overlap length($\Delta$L) at a critical gate bias point. In this paper, we conducted an experiment on two different C-V methods. L$_{eff}$ extracted from experiment is compared with L$_{eff}$ simulated from a two-dimensional (2-D) device simulator, and the accuracy of C-V method for L$_{eff}$ extraction is analyzed.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.679-682
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• 2003

Improvement in MOS fabrication technology have led to high-density high-performance integrated circuits with MOSFET channel lengths in the sub-micron range. For devices of the size, transistor characteristics become highly sensitive to effective channel length. We propose a new approach to extract the effective channel length of MOSFET by Capacitance-Voltage (C-V) method. Gate-to-Source, Drain capacitance ( $C_{gsd}$) are measured and the effective channel length can be extracted. In addition, compared to l/$\beta$ method and Terada method, which has been point out that it fails to extract the accurate effective channel length of the devices, we prove that our approach still works well for the devices with down to sub-micron regime.e.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.170-177
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• 2008

In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.130-133
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• 2011

A comparative study of two capacitance methods to measure the effective channel length in deep-submicron MOSFETs has been made in detail. Since the reduction of the overlap capacitance in the accumulation region is smaller than the addition of the inner fringe capacitance at zero gate voltage, the capacitance method removing the parasitic capacitance in the accumulation region extracts a more accurate effective channel length than the method removing that at zero gate voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.653-657
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• 2015

A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.26-32
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• 1998

We have studied how the characteristics degradation between effective mobility and field effect mobility of gate channel in p-MOSFET's affects the gate channel length being follow by increased stress time and increased drain-source voltage stress. The experimental results between effective and field-effect mobility were analyzed that the measurement data are identical at the point of minimum slope in threshold voltage, the other part is different, that is, the effective mobility it the faster than the field-effect mobility. Also, It was found that the effective and field-effect mobility. Also, It was found that the effective and field-effect mobility of p-MOSFET's with short channel are increased by decreased channel length, increased stress time and increased drain-source voltage stress.

• ETRI Journal
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• v.46 no.3
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• pp.392-403
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• 2024

Even though generalized frequency division multiplexing is an alternative waveform method expected to replace the orthogonal frequency division multiplexing in the future, its implementation must alleviate channel effects. Least-squares (LS), a low-complexity channel estimation technique, could be improved by using the discrete Fourier transform (DFT) without increasing complexity. Unlike the usage of the LS method, the DFT-based method requires the receiver to know the channel impulse response (CIR) length, which is unknown. This study introduces a simple, yet effective, CIR length estimator by utilizing LS estimation. As the cyclic prefix (CP) length is commonly set to be longer than the CIR length, it is possible to search through the first samples if CP is larger than a threshold set using the remaining samples. An adaptive scale is also designed to lower the error probability of the estimation, and a simple signal-to-interference-noise ratio estimation is also proposed by utilizing a sparse preamble to support the use of the scale. A software simulation is used to show the ability of the proposed system to estimate the CIR length. Due to shorter CIR length of rural area, the performance is slightly poorer compared to urban environment. Nevertheless, satisfactory performance is shown for both environments.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.1
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• pp.47-52
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• 2007

Organic field-effect transistors (OFETS) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with varying channel length. The CuPc FET device was made a top-contact type and the channel length was a $100\;{\mu}m,\;50\;{\mu}m,\;40\;{\mu}m,\;and\;30\;{\mu}m$ and the channel width was a fixed at 3 mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with varying channel length (L) and we calculated the effective mobility. Also, we measured a capacitance-voltage (C-V) by applied bias voltage with varying frequency at 43, 100, 1000 Hz.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.72-79
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• 1994

In this paper semi empirical models are presented for the hot electron induced threshold voltage shift(${\Delta}V_{t}$) and effective channel shortening length (${\Delta}L_{H}$) in degraded PMOSFET. Trapped electron charges in gate oxide are calculated from the well known gate current model and ΔLS1HT is calculated by using trapped electron charges. (${\Delta}L_{H}$) is a function of gate stress voltage such as threshold voltage shift and degradation of drain current. From the correlation between (${\Delta}L_{H}$) has a logarithmic function of stress time. From the measured results, (${\Delta}V_{t}$) and (${\Delta}L_{H}$) are function of initial gate current and device channel length.