• Journal of Power Electronics
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• v.16 no.1
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• pp.66-73
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• 2016

The quantity of alternating current (AC) leakage and the value of distortion factor in capacitor currents are discussed with regard to a new power component called variable capacitance device (VCD). This component has terminals for controlling its capacitance. Nonlinear dielectric characteristics are utilized in this device to vary the capacitance. When VCD operates in an AC circuit, the AC leakage from this device through direct current (DC) control voltage source increases according to the conditions of DC control voltage and so on. To solve this problem, we propose techniques for suppressing AC leakage. Although VCD has strong nonlinear characteristics, the current through the capacitor is not distorted significantly. The relations between AC leakage and the distortion in current waveforms are investigated. An application example for an AC power regulator is also introduced to evaluate the distortion in waveforms.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1912-1919
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• 2018

The output capacitance of power semiconductor devices is important in determining the switching losses and in the operation of some resonant converter topologies. Thus, it is important to be able to accurately determine the output capacitance of a particular device operating at elevated power levels so that the contribution of the output capacitance discharge to switch-on losses can be determined under these conditions. Power semiconductor switch manufacturers usually measure device output capacitance using small-signal methods that may be insufficient for power switching applications. This paper shows how first principle methods are applied in a novel way to obtain more relevant large signal output capacitances of Gallium-Nitride (GaN) FETs using the drain-source voltage transient during device switch-off numerically. A non-linear capacitance for an increase in voltage is determined with good correlation. Simulations are verified using experimental results from two different devices. It is shown that the large signal output capacitance as a function of the drain-source voltage is higher than the small signal values published in the data sheets for each of the devices. It can also be seen that the loss contribution of the output capacitance discharging in the channel during switch-on correlates well with other methods proposed in the literature, which confirms that the proposed method has merit.

• Journal of IKEEE
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• v.16 no.4
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• pp.283-289
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• 2012

In this paper, We proposed Separate Gate Technique(SGT) to improve the switching characteristics of Trench power MOSFET. Low gate-to-drain 전하 (Miller 전하 : Qgd) has to be achieved to improve the switching characteristics of Trench power MOSFET. A thin poly-silicon deposition is processed to form side wall which is used as gate and thus, it has thinner gate compared to the gate of conventional Trench MOSFET. The reduction of the overlapped area between the gate and the drain decreases the overlapped charge, and the performance of the proposed device is compared to the conventional Trench MOSFET using Silvaco T-CAD. Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) and Crss(reverse recovery capacitance : Cgd) are reduced to 14.3%, 23% and 30% respectively. To confirm the reduction effect of capacitance, the characteristics of inverter circuit is comprised. Consequently, the reverse recovery time is reduced by 28%. The proposed device can be fabricated with convetional processes without any electrical property degradation compare to conventional device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.331-341
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• 2013

In the present work, the effect of the gate-to-drain capacitance ($C_{gd}$) on the noise performance of a symmetric tied-gate $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}As$ double-gate HEMT is studied using an accurate charge control based approach. An analytical expression for the gate-to-drain capacitance is obtained. In terms of the intrinsic noise sources and the admittance parameters ($Y_{11}$ and $Y_{21}$ which are obtained incorporating the effect of $C_{gd}$), the various noise performance parameters including the Minimum noise figure and the Minimum Noise Temperature are evaluated. The inclusion of gate-to-drain capacitance is observed to cause significant reduction in the Minimum Noise figure and Minimum Noise Temperature especially at low values of drain voltage, thereby, predicting better noise performance for the device.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.818-822
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• 1987

Gate capacitances have been measured directly on small-geometry MOSFET's with the drain voltage as a parameter for various channel lengths and for p and n channel types and the characteristics have been compared with each other. The influence of 'hot carrier effect' of short channel devices on capaciatance has been compared with long channel devices. The results show that gate capacitance characteristics of short channel device deviate from those of long channel device. The accuracy of the measurement system is less than a few femto Farad, and the minimum geometry (W/L) of device for which reliable measurement can be obtained is 6/3.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.3
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• pp.209-213
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• 2007

The MOS gate capacitance model presented here is determined by directly solving the coupled Poisson equations on the poly and silicon sides, and includes the polysilicon (poly) gate depletion effect. Our compact gate capacitance model exhibits an excellent fit with measured data and parameter values extracted from data are physically acceptable. The data are collected from 0.5, 0.35, 0.25 and $0.18{\mu}m$ CMOS technologies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.1-7
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• 2008

In this work, a two dimensional, self-consistent Poisson-$Schr{\ddot{o}}dinger$ solver has been implemented to study C-V characteristics in nanometer scale MuGFETs with considering quantum effects. The quantum-mechanical effects on gate-channel capacitance for different device dimension and gate configurations of nanometer scale MuGFETs have been analyzed. It has been found that 4he gate-channel capacitance per unit gate area is increased as the device dimension decreases. For different gate configurations, the gate-channel capacitance is decreased with increase of effective gate number. Those resu1ts have been explained by the distribution profile of electron concentration in the silicon surface and inversion capacitance. The length of inversion-layer centroid has been calculated from inversion capacitance with device dimension and gate configurations.

• Polymer(Korea)
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• v.36 no.4
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• pp.519-524
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• 2012

Capacitance measurements of the polymer light-emitting diodes (PLEDs) with conjugated polyelectrolyte (CPE) electron transporting layers (ETLs) provide important information of device physics for understanding the function of CPEs as ETLs, together with current density-voltage-luminescence measurements. We investigated the counterion-dependent capacitance behaviors that present a highly negative or positive capacitance at the low frequency, and suggested different carrier injection mechanisms. Capacitance model study reveals that the electron injection mechanism can be described either by the dipole alignment scheme or by electronic charge carrier accumulation at the cathode/ETL/emission layer interfaces.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.224-236
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• 2013

This work presents a comparative study of four Double Gate tunnel FET (DG-TFET) architectures: conventional p-i-n DG-TFET, p-n-p-n DG-TFET, a gate dielectric engineered Heterogate (HG) p-i-n DG-TFET and a new device architecture with the merits of both Hetero Gate and p-n-p-n, i.e. HG p-n-p-n DG-TFET. It has been shown that, the problem of high gate capacitance along with low ON current for a p-i-n TFET, which severely hampers the circuit performance of TFET can be overcome by using a p-n-p-n TFET with a dielectric engineered Hetero-gate architecture (i.e. HG p-n-p-n). P-n-p-n architecture improves the ON current and the heterogeneous dielectric helps in reducing the gate capacitance and suppressing the ambipolar behavior. Moreover, the HG architecture does not degrade the output characteristics, unlike the gate drain underlap architecture, and effectively reduces the gate capacitance.