• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.639-645
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• 2015

Checksum and residue checking accelerators were implemented on a Nios II core-based platform according to component method, in which the corresponding hardware was implemented with HDL coding, a custom instruction method, in which the instruction set of the processor was extended, and the C2H method, in which the corresponding logic was automatically created by the C2H compiler. The processing results from each accelerator for each algorithm were then examined and compared. The results of the comparison showed that the accelerator implemented with the C2H method is the fastest in terms of the execution time, and the accelerator with custom instruction requires the least add-on from the viewpoint of add-on hardware.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.414-417
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• 1988

Recently PLC pursues faster scanning time, circuit confidence, reliability improvement, and smaller size. To obtain above all merit, custom IC(Gate Array) is developed. Custom IC includes 5 main blocks and 2 auxiliary blocks. The 5 main blocks process faster sequential instruction execution by only logic gate using hexa instruction code system. And the 2 auxiliary blocks generate baud rate clock (153.6 KHz, 76.8KHz) to communicate between PLC and computer or programmers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.51-58
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• 2011

Extensible processors provide an efficient mechanism to boost the performance of the whole system without losing much flexibility. However, due to the intense demand of low cost and power consumption, customizing an embedded system has been more difficult than ever. In this paper, we present a framework for custom instruction generation considering both area constraints and resource sharing. We also present how we can speed up the process through pruning and library-based design space exploration.

• Journal of Korea Society of Digital Industry and Information Management
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• v.11 no.3
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• pp.31-43
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• 2015

In this paper, we discuss a code generation technique for custom transport triggered architecture (TTA) from a high-level language structure. This methodology is implemented by using TTA-based Co-design Environment (TCE) tool. The results show how the scheduler exploits instruction level parallelism in the custom target architecture and source program. Thus, the scheduler generates parallel TTA instructions using lower cycle counts than the sequential scheduling algorithm. Moreover, we take Tensilica tool to make a comparison with TCE. Because of the efficiency of TTA, TCE takes less execution cycles compared to Tensilica configurations. Finally, this paper shows that it requires only 7 cycles to generate the parallel TTA instruction set for implementing Cyclic Redundancy Check (CRC) applications as an input design, and presents the code generation technique to move complexity from the processor software to hardware architecture. This method can be applicable lots of channel Codecs like CRC and source Codecs like High Efficiency Video Coding (HEVC).

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• The Journal of Korean Academy of Prosthodontics
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• v.51 no.4
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• pp.276-283
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• 2013

Purpose: The purpose of this study was to investigate the fit and screw joint stability between Ready-made abutment and CAD-CAM custom-made abutment. Materials and methods: Osstem implant system was used. Ready-made abutment (Transfer abutment, Osstem Implant Co. Ltd, Busan, Korea), CAD-CAM custom-made abutment (CustomFit abutment, Osstem Implant Co. Ltd, Busan, Korea) and domestically manufactured CAD-CAM custom-made abutment (Myplant, Raphabio Co., Seoul, Korea) were fabricated five each and screws were provided by each company. Fixture and abutments were tightening with 30Ncm according to the manufacturer's instruction and then preloding reverse torque values were measured 3 times repeatedly. Kruskal-Wallis test was used for statistical analysis of the preloading reverse torque values (${\alpha}=.05$). After specimens were embedded into epoxy resin, wet cutting and polishing was performed and FE-SEM imaging was performed, on the contact interface. Results: The pre-loading reverse torque values were $26.0{\pm}0.30Ncm$ (ready-made abutment; Transfer abutment) and $26.3{\pm}0.32Ncm$ (CAD-CAM custom-made abutment; CustomFit abutment) and $24.7{\pm}0.67Ncm$ (CAD-CAM custom-made abutment; Myplant). The domestically manufactured CAD-CAM custom-made abutment (Myplant abutment) presented lower pre-loading reverse torque value with statistically significant difference than that of the ready-made abutment (Transfer abutment) and CAD-CAM custom-made abutment (CustomFit abutment) manufactured from the same company (P=.027) and showed marginal gap in the fixture-abutment interface. Conclusion: Within the limitation of the present in-vitro study, in domestically manufactured CAD-CAM custom-made abutment (Myplant abutment) showed lower screw joint stability and fitness between fixture and abutment.

• The Journal of Korean Academy of Prosthodontics
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• v.38 no.5
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• pp.640-649
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• 2000

In the restoration of endodontically treated teeth, carbon fiber post was recently introduced. The purpose of this in vitro study was to investigate the fracture strength of teeth restored with a pre-fabricated carbon fiber post in comparison with teeth restored with a prefabricated titanium post & custom cast gold post after cyclic loading in the different environment. A total of 30 recently extracted human central incisors of similar dimension with crowns removed were used. All teeth were placed into acrylic blocks and every steps for post and core fabrication were made accord-ing to manufacture's instruction. The post length and core dimensions were standardizd. All teeth were divided into 6 groups: 1) carbon fiber post / atmosphere, 2) titanium post / atmosphere, 3) gold post / atmosphere, 4) carbon fiber post / wet, 5) titanium post / wet, 6) gold post / wet. Carbon fiber post and titanium post were cemented in place using resin cement and cores were fabricated with Ti-Core. Custom cast gold post was made from Duralay pattern resin and cemented using resin cement, too. All specimens were thermocycled 10,000 times. After 50,000 cyclic loading, failure strength was measured using Instron testing machine. Kruskal-Wallis test followed by Mann-Whitney test was used to compare the mean fracture strength. Results were as follows : 1. All specimens showed lower fracture strength in wet environment after cyclic loading than in atmosphere condition, but did not reveal a significant difference. 2. There was no significant difference between carbon fiber post specimen and titanium post specimen in the same environment. 3. Gold cast post specimen showed significant different greater fracture strength than those of others in the same environment. 4. Carbon fiber post specimen showed no root fracture.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.517-530
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• 1994

In this paper, design of small microprocessor unit is implemented using research purpose VHDL and CAD tools by top-down design method. For this, original basic MPU and its pipelining architectures are suggested. Once, design target, instruction sets, architecture are decided, the operation is confirmed by C language simulation, and then the operation is confirmed by checking internal register contents for given inputs in the case of VHDL simulation. Then, design layouts are made by full/semi-custom design methods by research CAD tools and related simulation is implemented. The feasibility of suggested pipelined structure for performance improvement is confirmed by simulation, and related problems and future research directions are discussed. In conclusion, the MPU design methodology is set up and the design change of architecture is possible by this paper.

• Journal of IKEEE
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• v.22 no.1
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• pp.87-92
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• 2018

Like CPUs, regular expression processors that perform regular expression pattern matching using instructions have been proposed recently. Of these, only REMPc provides features for character class matching. In this paper, we propose an architecture for efficient character class matching in a regular expression processor, which use character class bitmap format in a instruction operand field and implement the hard-wired character class comparator for several frequently used character classes. Using the proposed method, most of the character classes used in Snort rule can be represented by an operand or an instruction. Thus, character class matching can be performed more efficiently in the proposed archiecture than in REMPc.