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http://dx.doi.org/10.17662/ksdim.2015.11.3.031

A Custom Code Generation Technique for ASIPs from High-level Language  

Alam, S.M. Shamsul (Khulna대학교 전자통신공학과)
Choi, Goangseog (조선대학교 정보통신공학과)
Publication Information
Journal of Korea Society of Digital Industry and Information Management / v.11, no.3, 2015 , pp. 31-43 More about this Journal
Abstract
In this paper, we discuss a code generation technique for custom transport triggered architecture (TTA) from a high-level language structure. This methodology is implemented by using TTA-based Co-design Environment (TCE) tool. The results show how the scheduler exploits instruction level parallelism in the custom target architecture and source program. Thus, the scheduler generates parallel TTA instructions using lower cycle counts than the sequential scheduling algorithm. Moreover, we take Tensilica tool to make a comparison with TCE. Because of the efficiency of TTA, TCE takes less execution cycles compared to Tensilica configurations. Finally, this paper shows that it requires only 7 cycles to generate the parallel TTA instruction set for implementing Cyclic Redundancy Check (CRC) applications as an input design, and presents the code generation technique to move complexity from the processor software to hardware architecture. This method can be applicable lots of channel Codecs like CRC and source Codecs like High Efficiency Video Coding (HEVC).
Keywords
Transport Triggered Architecture(TTA); TTA-based Co-design Environment (TCE); Instruction Level Parallelism (ILP); Architecture Definition File(ADF); Implementation Definition File(IDF);
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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