1 |
C. Hendrik, "Transport Triggered Architectures Design and Evaluation," Ph. D Dissertation, Technical University of Delft Standford University, Delft, Netherlands, 1995.
|
2 |
P. Jaaskelainen, "From Parallel Programs to Customized Parallel Processors," Ph. D Dissertation, Tampere University of Technology, Tampere, Finland, 2012.
|
3 |
P. Jaaskelainen, "Instruction Set Simulator for Transport Triggered Architectures," Master Dissertation, Tampere University of Technology, Tampere, Finland, 2005.
|
4 |
Alam S. Shamsul, Choi GoangSeog, "Response of Transport Triggered Architectures for High-speed Processor Design," IEICE Electronics Express Vol. 10, No. 5, 2013, pp. 1-6.
|
5 |
Metsahalme, "Instruction Scheduler Framework for Transport Triggered Architectures," Master Dissertation, Tampere University of Technology, Tampere, Finland, 2008.
|
6 |
P. Jaaskelainen, V. Guzma, A. Cilio, and J. Takala, "Codesign Toolset for Application-Specific Instruction-Set Processors," Proceedings of the Conference on Multimedia on Mobile Devices, SPIE, Nov 2007.
|
7 |
Tensilica. com, ConnX D2 DSP Engine. http://www.tensilica.com/uploads/pdf/connx_d2_pb.pdf, 2012.
|
8 |
Tensilica. com, ConnX D2 DSP Engine, http://www.tensilica.com/uploads/pdf/HiFi_2_product_brief.pdf, 2012.
|
9 |
Tensilica Diamond Standard Controller Data Book. http://www.tensilica.com/products/diamonds#designtools, 2012.
|
10 |
Tensilica. com, Xtensa 7 Product Brief. http://www.tensilica.com/uploads/pdf/xtensa_7.pdf, 2012.
|
11 |
하산타릭, 최광석, "효율적인 정도 생성기 및 새로운 순열 기법을 가진 LT 코덱구조," 디지털산업정보학회논문지, 제10권, 제4호, 2014, pp. 117-125.
DOI
|
12 |
무하마드 아심, 최광석, "무선채널에서 결합 분수 부호들의 성취율 평가," 디지털산업정보학회 논문지, 제8권, 제1호, 2012, pp. 147-155.
|