[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.5762/KAIS.2015.16.1.639

Comparison of Nios II Core-based Accelerators Niod II 코어기반 가속기 비교

Song, Gi-Yong (School of Electronics Engineering, Chungbuk National University)

Publication Information

Journal of the Korea Academia-Industrial cooperation Society / v.16, no.1, 2015 , pp. 639-645 More about this Journal

Abstract

Checksum and residue checking accelerators were implemented on a Nios II core-based platform according to component method, in which the corresponding hardware was implemented with HDL coding, a custom instruction method, in which the instruction set of the processor was extended, and the C2H method, in which the corresponding logic was automatically created by the C2H compiler. The processing results from each accelerator for each algorithm were then examined and compared. The results of the comparison showed that the accelerator implemented with the C2H method is the fastest in terms of the execution time, and the accelerator with custom instruction requires the least add-on from the viewpoint of add-on hardware.

Keywords

accelerator; checksum; Nios II core; residue checking;

Citations & Related Records

Reference

1	Li Junwei, Yan Han, "The Development of a SOPC system based Nios II," Sciencepaper Online, 2007.
2	Yu-Chih Liu, M, Hardware objects & accelerators on Nios II platform, Thesis for Master of Science, Department of Computer Science and Engineering ,Tatung University, 2009.
3	Altera Corporation, "Avalon Interface Specifications," http://www.altera.com/literature/manual/mnl_avalon_spec.pdf,May. 2013.
4	Altera Corporation, "Nios II Custom Instruction User Guide," http://www.altera.com/literature/ug/ug_nios2_custom_instruction.pdf, January. 2011.
5	Altera Corporation, "Nios II C2H Compiler User Guide," http://www.altera.com/literature/ug/ug_nios2_c2h_compiler.pdf, November. 2009.
6	Bob Zeidman Verilog Designer's Library, Prentice Hall PTR, pp. 261-268, 1999.
7	Douglas J. Smith HDL Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & FPGAs using VHDL or Verilog, Doone Publications, pp. 279-312, 1999.