• Ocean and Polar Research
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• v.29 no.4
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• pp.283-295
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• 2007

We investigated the longitudinal variations in zooplankton abundances and their related physicochemical properties at nine stations located between $136^{\circ}W$ and $128^{\circ}W$ at $10.5^{\circ}N$ in the northeastern Pacific in summer 2004. Temperature, salinity, inorganic nutrients, chlorophyll-a (hereafter chl-a) and zooplankton ($>200\;{\mu}m$) were sampled within the depth from the surface to 200 m depth at $1^{\circ}$ longitude intervals. Zooplankton($>200\;{\mu}m$) samples were vertically collected at two depth intervals from surface to 200 m, consisting of surface mixed and lower layers (thermocline$\sim$200 m). Longitudinal distributional pattern of hydrological parameters (especially salinity) was physically influenced by the intensity of westward geostrophic current passage relating to the NEC (North Equatorial Current). Data from the longitudinal survey showed clear zonal distributions in the hydrological parameters(temperature, salinity and nutrients). However, spatial patterns of the chl-a concentrations and zooplankton abundances were mostly independent of the zonal distributions of hydrological parameters. The two peaks of zooplankton abundance in the surface mixed layer were characterized by different controlling factors such as bottom-up control from nutrients to zooplankton ($129^{\circ}W$) and accumulation by increment of friction force and taxonomic interrelationship ($133^{\circ}$ and $134^{\circ}W$). Divergence-related upwelling caused introduction of nutrients into surface waters leading to the increment of chl-a concentration and zooplankton abundances ($129^{\circ}W$). Increased friction force in relation to reduced flow rates of geostrophic currents caused accumulation of zooplankton drifting from eastern stations of study area($133^{\circ}$ and $134^{\circ}W$). Besides, high correlation between immature copepods and carnivorous groups such as chaetognaths and cyclopoids also possibly contributed to the enhanced total abundance of zooplankton in the surface mixed layer (p<0.05). Zooplankton community was divided into three groups (A, B, C) which consecutively included the eastern peak of zooplankton($129^{\circ}W$), the western peak($133^{\circ}$ and $134^{\circ}W$) and high nutrient but low chl-a concentration and zooplankton abundance ($136^{\circ}W$). Moreover, Group B corresponded to the westward movement of low saline waters(<33.6 psu) from 128 to $132^{\circ}W$. In summary, longitudinal distributions of zooplankton community was characterized by three different controlling factors: bottom-up control ($129^{\circ}W$), accumulation by increased friction force and relationships among zooplankton groups ($133^{\circ}$ and $134^{\circ}W$), and mismatch between hydrological parameters and zooplankton in the high nutrient low chlorophyll area ($136^{\circ}W$) during the study period.

• KDI Journal of Economic Policy
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• v.32 no.4
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• pp.153-195
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• 2010

The recent global financial crisis has been the outcome of, among other things, the mismatch between institutions and the reality of the market in the current global financial system. The International financial institutions (IFIs) that were designed more than 60 years ago can no longer effectively meet the challenges posed by the current global economy. While the global financial market has become integrated like a single market, there is no international lender of last resort or global regulatory body. There also has been a rapid shift in the weight of economic power. The share of the Group of 7 (G7) countries in global gross domestic product (GDP) fell and the share of emerging market economies increased rapidly. Therefore, the tasks facing us today are: (i) to reform the IFIs -mandate, resources, management, and governance structure; (ii) to reform the system such as the international monetary system (IMS), and regulatory framework of the global financial system; and (iii) to reform global economic governance. The main focus of this paper will be the IMS reform and the role of the Group of Twenty (G20) summit meetings. The current IMS problems can be summarized as follows. First, the demand for foreign reserve accumulation has been increasing despite the movement from fixed exchange rate regimes to floating rate regimes some 40 years ago. Second, this increasing demand for foreign reserves has been concentrated in US dollar assets, especially public securities. Third, as the IMS relies too heavily on the supply of currency issued by a center country (the US), it gives an exorbitant privilege to this country, which can issue Treasury bills at the lowest possible interest rate in the international capital market. Fourth, as a related problem, the global financial system depends too heavily on the center country's ability to maintain the stability of the value of its currency and strength of its own financial system. Fifth, international capital flows have been distorted in the current IMS, from EMEs and developing countries where the productivity of capital investment is higher, to advanced economies, especially the US, where the return to capital investment is lower. Given these problems, there have been various proposals to reform the current IMS. They can be grouped into two: demand-side and supply-side reform. The key in the former is how to reduce the widespread strong demand for foreign reserve holdings among EMEs. There have been several proposals to reduce the self-insurance motivation. They include third-party insurance and the expansion of the opportunity to borrow from a global and regional reserve pool, or access to global lender of last resort (or something similar). However, the first option would be too costly. That leads us to the second option - building a stronger globalfinancial safety net. Discussions on supply-side reform of the IMS focus on how to diversify the supply of international reserve currency. The proposals include moving to a multiple currency system; increased allocation and wider use of special drawing rights (SDR); and creating a new global reserve currency. A key question is whether diversification should be encouraged among suitable existing currencies, or if it should be sought more with global reserve assets, acting as a complement or even substitute to existing ones. Each proposal has its pros and cons; they also face trade-offs between desirability and political feasibility. The transition would require close collaboration among the major players. This should include efforts at the least to strengthen policy coordination and collaboration among the major economies, and to reform the IMF to make it a more effective institution for bilateral and multilateral surveillance and as an international lender of last resort. The success on both fronts depends heavily on global economic governance reform and the role of the G20. The challenge is how to make the G20 effective. Without institutional innovations within the G20, there is a high risk that its summits will follow the path of previous summit meetings, such as G7/G8.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.27-35
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• 2008

This work proposes a 14b 150MS/s 0.13um CMOS ADC for SDR systems requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC employs a calibration-free four-step pipeline architecture optimizing the scaling factor for the input trans-conductance of amplifiers and the sampling capacitance in each stage to minimize thermal noise effects and power consumption at the target resolution and sampling rate. A signal- insensitive 3-D fully symmetric layout achieves a 14b level resolution by reducing a capacitor mismatch of three MDACs. The proposed supply- and temperature- insensitive current and voltage references with on-chip RC filters minimizing the effect of switching noise are implemented with off-chip C filters. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates a measured DNL and INL within 0.81LSB and 2.83LSB, at 14b, respectively. The ADC shows a maximum SNDR of 64dB and 61dB and a maximum SFDR of 71dB and 70dB at 120MS/s and 150MS/s, respectively. The ADC with an active die area of $2.0mm^2$ consumes 140mW at 150MS/s and 1.2V.

• The Korean Journal of Nuclear Medicine
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• v.27 no.2
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• pp.155-160
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• 1993

The identification of viable myocardium in patients with coronary artery disease and left ventricular dysfunction is an issue of increasing clinical relavance in the current era of myocardial revascularization. There are at least two forms of reversible myocardial dysfunction. Early reperfusion does not always lead to immediate functional improvement; rather, the return of contractility in tissue salvaged by reperfusion is delayed for hours, days or even weeks, a phenomenon that has been termed "stunned myocardium". Some patients with coronary artery disease show myocardial dysfunction at rest which are associated with reduced perfusion, and which disappear after revascularization; this phenomenon has been termed "hibernating myocardium". Recently, cardiac imaging techniques that evaluate myocardial viability on the basis of perfusion-contraction mismatch and inotropic reserve have gained substantial popularity and clinical success. This review focus on the application of $^{201}TI$ and $^{99m}Tc-MIBI$ to address myocardial viability in patients with hibernating and stunned myocardium. It is clear that 4-hour redistribution images of $^{201}TI$ underestimate ischemia and overestimate scar. Delayed imaging and reinjection imaging have been developed for the assessment of viability. Among many protocols suggested, stress-redistribution-reinjection imaging gained most popularity. Although $^{99m}Tc-MIBI$ could identify myocardial viability, $^{201}TI$ reinjection technique was regarded as superior to it. In conclusion, $^{201}TI$ stress, 4-hr rest redistribution, and reinjection imaging technique may be the most preferable method for evaluation of myocardial viability.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Journal of the Korean Electrochemical Society
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• v.5 no.3
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• pp.125-130
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• 2002

An attempt was made for the application of porous reticular metal to a heat dissipation material in semiconductor process. For this aim, the electrodeposition of Fe/Ni alloy on the porous reticular Cu has been performed to minimize the thermal expansion mismatch between Cu skeleton and electronic chip. Preliminary tests for the electrodeposition of Fe/Ni alloy layer were conducted by using standard Hull Cell to examine the effect of current density on the composition of alloy layer. It seemed that mass transfer affected significantly the composition of Fe/Ni layer due to anomalous codeposition in the electrodeposition of Fe/Ni alloy. A paddle type stirring bath, which was employed to control the mass transfer of electrolyte in the work, was found to allow the electrodeposition Fe/Ni with a precise composition. result showed that the thermal expansion of Fe/Ni alloy layer was much lower than that of pure copper. From the tests of heat dissipation by using the apparatus designed in the work the heat dissipation material fabricated in the work showed the excellent heat dissipation capacity, namely, more than two times as compared to that of pure copper plate.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.60-68
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• 2008

This work describes a re-configurable 10MS/s to 100MS/s, low-power 10b two-step pipeline ADC operating at a power supply from 0.5V to 1.2V. MOS transistors with a low-threshold voltage are employed partially in the input sampling switches and differential pair of the SHA and MDAC for a proper signal swing margin at a 0.5V supply. The integrated adjustable current reference optimizes the static and dynamic performance of amplifiers at 10b accuracy with a wide range of supply voltages. A signal-isolated layout improves the capacitor mismatch of the MDAC while a switched-bias power-reduction technique reduces the power dissipation of comparators in the flash ADCs. The prototype ADC in a 0.13um CMOS process demonstrates the measured DNL and INL within 0.35LSB and 0.49LSB. The ADC with an active die area of $0.98mm^2$ shows a maximum SNDR and SFDR of 56.0dB and 69.6dB, respectively, and a power consumption of 19.2mW at a nominal condition of 0.8V and 60MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.