• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.41-45
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• 2017

This paper presents a method of constructing the efficiency multiple output switching function of the combinational logic systems. The proposed method reduce the optimized input variable pair and output variable pair after we obtained the final multiple output switching function which was time based multiplexing and obtained the common multiple end node extension logic decision diagram. Also the proposed method have an advantage of the cost, input-output node number, circuit simplification, increment of the arithmetic speed, and more regularity and extensibility compare with previous method.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.220-223
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• 2002

The digital logic systems(DLS) is classified into digital combinational logic systems(CDLS) and digital sequential logic systems(SDLS). This paper presents a method of constructing the digital sequential logic systems without feedback. Firstly we assign all elements in Finite Fields to P-valued digit codes using mathematical properties of Finine Fields. Also, we discuss the operarional properties of the building block T-gate that is used to realizing digital sequential logic systems over Finite Fields. Then we realize the digital sequential logic systems without feedback. This digital sequential logic systems without feedback is constructed ny following steps. Firstly, we assign the states in the state-transition diagram to state P-valued digit dodo, then we obtain the state function and predecessor table that is explaining the relationship between present state and previous states. Next, we obtained the next-state function and predecessor table. Finally, we realize the circuit using T-gate and decoder.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1839-1849
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• 1989

An optimal variable assignment algorithm is presented as a decomposition method of MVL functions. A given 3-valued combinational logic function is disintegrated into subfunction composed of the function dependant relation, then extracted implicant output elements from subfunctions are assigned to a T-gates. As a circuit implementation tool, a programmable integarated T-gate module is proposed, and the construction procedure of combinational MVL functions is systematized in each step. This method is expected to give properties of the systematic procedure, possibility of T-gate number reduction, unification of module, and flexibility of module composition. Specially variable decomposition method can be pointed out as an approach to solving the limitation problem of the input and output terminal number in VLSI implementations.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.2
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• pp.47-55
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• 1984

This paper is concerned with a computer-aided state assignment, that is, coding race-free internal states of asynchronous sequential circuits, and a method for minimizing the combinational network of asynchronous sequential circuits. The FORTRAN version of the peoposed algorithm results in race-free state assignments and reduction of the number of connections and gates with near minimal hardware cost. Some examples are designed by the proposed computer program to illustrate the algorithm in this paper. Finally, results are compared with those of the other methods.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.177-185
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• 1996

This paper describes several algorithms for technolgoy mapping of logic functions into interesting and popular FPGAs that use look-up table memories. In order to improved the technology mapping for FPGA, some existing multi-level logic synthesis, decomposition reduction and packing techniques are analyzed and compared. And then new algorithms such as merging fanin, unified reduction and multiple disjoint decomposition which are used for combinational logic design, are proposed. The cost function is used to minimize the number of CLBs and edges of the network. The cost is a linear combination of each weight that is given by user. Finally we compare our new algorithm with previous logic design technique. In an experimental comparison our algorithm requires 10% fewer CLB and nets than SIS-pga.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1613-1621
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• 1997

Many studies on internal data expression to process logic functions efficiently on computer have been doing actively. In this paper, we propose an efficient logic function manipulation system made on the Objected-Oriented manner, where Binary Decision Diagrams(BDD's) are adopted for internal data espressionof logic functions. Thus it is easy to make BDD's presenting combinational problems. Also, we propose a method of applying filtering function for reducing the size of BDD's instead of attributed bits, and add it to the mainpultion system. As a resutls, the space of address is expanded so that the number of node that can be used in the mainpulation system is increased up to 2/sup 27/. Finally, we apply the implemented system to One-Shot state assignment problems of asynchronous sequential circuits and show that it is efficient for the filtering method to reduce the size of BDD's.

• Journal of Electrical Engineering and Technology
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• v.4 no.4
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.29-38
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• 1999

This paper presents a new algorithm RICP(Redundancy Identification using Critical-pair Paths) to identify untestable faults in combinational logic circuits. In a combinational logic circuit, untestable faults occurred by redundancy of circuits. The redundancy of a circuit can be detected by analyzing areas of fanout stem and reconvergent gates. The untestable faults are identified by analyzing stem area using Critical-Pair path which is an extended concept of critical path. It is showed that RICP is better than FIRE(Fault Independent REdundancy identification) algorithm in efficiency. The performance of both algorithms was compared using ISCAS85 bench mark testing circuits.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.82-89
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• 1993

In this paper, we proposed the autonomous algorithm of pseudo-exhaustive testing for the multi-level combinational logic circuits. For the processing of shared-circuit that existed in each cone-circuit when it backtracked the path from PO to PI of CUT at the conventional verification testing, the dependent relation of PI-P0 is presented by a dependence matrix so it easily partitioned the sub-circuits for the pseudo-exhaustive testing. The test pattern of sub-circuit's C-inputs is generated using a binary counter and the test pattern of I-inputs is synthesized using a singular cover and consistency operation. Thus, according to the test patterns presented with the recipe cube, the number of test pattrens are reduced and it is possible to test concurrently each other subcircuits. The proposed algorithm treated CUT's net-list to the source file and was batch processed from the sub-circuit partitioning to the test pattern generation. It is shown that the range of reduced ration of generated pseudo-exhaustive test pattern exhibits from 85.4% to 95.8% when the average PI-dependency of ISACS bench mark circuits is 69.4%.